data bus width difference between processor and memory

[fragnen]

A processor has a 64 bit data bus and with this 64 bit data bus the processor want to write into a memory whose data bus width is 16. What can be done with the processor to write into this memory which has data bus width of 16 so thar there is no data loss of the data that is coming out of the 64 bit width data bus of processor?

 

[barry]

Use a multiplexer and 4 consecutive writes.

But if you're designing an ASIC, why do you have this problem?

 

[dpaul]

Problems are everywhere for a person who does not know how to or perhaps does not want to use a search engine to find out answers for questions.

 

[Akanimo]

You can declare a 64 but register to temporarily store the processor data. Use a finite state machine with at least an 'enable' signal and a 'done' signal to store consecutive 16 bits into consecutive memory location with four write cycles.

 

[dick_freebird]

Whose choice was it to use "a" memory of stupid-short width, and with lagging-tech 16b memory being surplus dirt why cannot you just buy 3 more?

There's material cost and then there's sitting around engineering cost. Get it done

 

[FvM]

Presume it's just an exercise problem. Unfortunately important information is missing, e.g. async or sync bus interface, does it expose a wait request input?