Data bits swap in PCB layout of SDRAM DDRL3L and length matching

[engr_joni_ee]

Hi,

I am using SDRAM DDR3L ( MT41K256M16L) in my PCB design with ZYNQ 7030. I am wondering if it is possible to swap some data bit traces of SDRAM DDR3L ( MT41K256M16L) in PCB layout ? The data bits of are from DQ0 to DQ15 and I am using only one SDRAM.

Is it necessary to match the length of all the data bit traces in PCB layout ? If yes then what is the tolerance +/- in th ? Is t possible to introduce delays in some data bit lies in the firmware design ?

 

[FvM]

You noticed Xilinx UG586? It gives the 7series design requirements for memory interfaces. Generally, you can relax matching requirements when running the memory below maximal speed. Other than address lines, data lines have no specific meaning and can be swapped.

 

[barry]

There are IDELAY and ODELAY elements in the FPGA that can be used to compensate for variations in trace length.

 

[engr_joni_ee]

I am thinking if we swap some address lines in the RAM chip than physically the data will store at a different location and if we read from same location the data contents will be the same, it just come from different location.

Similarly, if we swap some data lines than the data bits will be swap on physical location when writing the data but if we read the data with same swap than we get the same data in firmware.

If there is only one RAM chip in the PCB design then we can swap address lines and also swap data lines according to the logic above. What is your say on it ?

 

[KlausST]

Hi,


SDRAMs have "commands" and need refresh. Thus you have to treat all related signal correctly.

A quick view into the datasheet shows that this SDRAM commands use Adress lines, thus you must not "modify" their order.

Klaus