basically I have in mind an amplifier which first amplifies a photodiode current trhough a darligton pair, then I use two stages of collector follower amplifier to convert the signal in a sufficient voltage level for further processing and I am trying to see how it is possible to make an estimation of a darligton pair bandwidth
The input current pulse is a 2.8MHz ~mA pulse which simulates the current response of the photodiode and this is implemented with a BJT component.
Q1 to Q2 collector is a correct connection for a Darlington pair.
If he connects Q1 collector to +5V there is nothing to limit the current thru Q1 and the Base/Emitter of Q2.
OK, but the problem remains:
What he wants is that when Q1 and Q2 switch on, they switch off Q3.
But that won't work because the voltage on the collector of Q1 can't go low enough, Q1 will saturate.
In the present circuit there's no reasonable purpose of a darlington stage. It can be also expected that the circuit behaviour will be dominated by other transistor parameters than ft, e.g. switching delay caused by charge storage.
I know how to get the BW by ltspice but I do not know to describe it in terms of theory (for Darligton pair),
by the way I am getting a 2.8MHz 0 to 5 V square pulse as desired (output) what is the main problems you suggest?
the first BJT is supposed to simulate the current produced by photoreceivers which receive a pulsed signal the rest of the amplifier functions like a transimpedance amplifier
hi 88,
If you post your LTS circuits 'asc' file I will run the Sim, then we we can discuss the problems using a common reference.
If the site software does not allow 'asc' file uploads, change the file extension to .txt.
E