Can anyone suggest me how to create a damped sinosoid source in cadence.
I was using a simple vsin source in which damping factor is one option putting a value less than one ideally it should work but its not working in my case.
You can generate a DS using an RLC circuit (see wikipedia) and driving it with a square wave. You should probably buffer the output with an ideal buffer too. The only problem you will have is that the DS will reverse polarity on each clock edge (positive will make the first oscillation go positive and a negative edge will make the first oscillation go negative).
Can anyone suggest me how to create a damped sinosoid source in cadence.
I was using a simple vsin source in which damping factor is one option putting a value less than one ideally it should work but its not working in my case.