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dac8004 SPI settings options

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yefj

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I think there is confusion over the SYNC signal. It doesn't switch between SPI and 'UART like' modes, it acts as a reset to synchronize the data transfer if the clock is continuous. Normal SPI would only send clock pulses during the data transfer, if I'm reading the data sheet correctly, the clock can be continuous on this device and SYNC can be used to 'frame' the transfer.
I confess I have never used one so this is gleaned from a quick glance at the data sheet.

Brian.
 
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    yefj

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Looking at Section 8.4.1.1 amd 8.4.1.1.1 of the referenced data sheet, the SYNC signal seems to operate in the same way as the \CS\ signal would.
What is a bit confusing is that there is a 'framed sync' SPI mode (as used by some manufacturers) where the clock is continuous but there is a single pulse either before the first valid clock or coinciding with it that tells the slave to start the exchange (i.e. marks the start of a data frame). This is different (i.e. it is a single clock width) whereas the device in question needs its SYNC to be low for (at least) the entire exchange. (I've used this framed SPI mode with the AMBE2020 codec chip.)
It seems to me that all you need to do is to treat this device as a 'normal' SPI slave.
Susan
 
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Hello , Yes want is the clock rate allowed for this device.
In the datasheet they only specify minimums.
What could be done to see the maximum clock rate?
Thanks.
1723720646136.png
 
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yefj said:
Hello , Yes want is the clock rate allowed for this device.
In the datasheet they only specify minimums.
What could be done to see the maximum clock rate?
Thanks.
View attachment 193068
Click to expand...
Minimum cycle time defines maximum clock rate.

Frequency = 1/period, remember?
 
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Hello,given the following diagrm from the datasheet I am not sure regarding clock data relations.
What is the ,clock polarity,clock phase,MSB first or not?
Thanks.

1723824882605.png
 
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What is the polarity and phase when we read on the middle on the falling edge ?
Thanks.
 
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The rises and falls in the diagram are all on the same time scale and start at the same time. All you have to do is draw (or imagine) a line dropped from the top line to see where all the other signals align with it.

Look at the clock signal where the dotted line drops down from it, you can see it lines up with the middle of the data bits D31 and D30 (and so on). The time from /SYNC going low (start of a transfer) to the first data sample is "tsu" and the first bit is sampled is on the falling edge of SCLK. The data has to be stable at least "tsu1" before the sample is taken. I'm guessing the "tsu" is an abbreviation of "time set up".

It also clearly shows D31 comes first and D0 last so it must be MSB first.

Brian.
 
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