DAC unit cap selection for SAR ADC

Hi,

I am designing a 12 bit SAR ADC, for that I need to select minimum unit capacitor for the DAC, And I am using sqrt(KT/C)< LSB/2 formula to calculate the capacitor value. The obtained capacitor value minimises the thermal noise impact, what about the other parameters like mismatch etc. and how they affects the capacitor value? How to select the capacitor value over these effects? or how to overcome from these effects?
Is there any formula to calculate effective minimum capacitor value?

please help me to find answer.

I am sad I don't have knowledge about it, it sounds interesting, but your equation seems vague in terms of left side / right side units.
I guess there are some extra behind them, which you understand, and my suggestion if you could calculate any reasonable theoretical C value from above share it us, then we can suggest maybe how far you from viability or we could share some experiences maybe that for a desired technology is it solvable to fight off the parasitics or mismatch effect.

Using the kT/C noise to calculate the unit cap is a reasonable approach. MOM caps usually used in the design of the cap dac for SARs match pretty well, maybe up to 10 bit accuracy and they keep their matching for many years. For 12 bit dac you may need to think of some sort of calibration for the first 2-3 MSB caps. Or use redundancy in the dac which will increase the physical number of bits but will take care of mismatch and settling errors.

A high attention should be paid to wiring parasitics - which may destroy your matching / binary weighting of the capacitors in the capacitor bank.
Use field solver (built-in in all standard parasitic extraction tools) and tighten its accuracy to a high level (0.1%, 0.01%, etc. - depending on your matching requirements).

Thank you

In some document I found a formula to calculate unit capacitance in mismatch perspective. for that I want technology matching coefficient constant (Kσ).
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please help me that how to find that constant.

Ask the fab. they should know it.

Besides thermal noise you care about charge injection
from the switches, that probably dwarfs thermal noise.
Thermal noise formula would be a minimum starting point,
what you find for Qsw and its variation w/ common mode,
PVT & MM etc will probably drive the unit C upward until
you are either comfortable with tolerances or constrained
by allotted layout area (then, tough choices or better
circuit design details).

Fab will not know anything about what makes a N-bit DAC
meet spec, unless they are (1) seeing that kind of circuitry
and (2) actually talking to designers and product development
/ yield engineering folks from the product side of the house.
A pure-play foundry for its "digital" nodes probably has no
good info for you, and you'd try to get a test chip on a
multiproject run to tease out these issues and design options'
key sensitivities. One advertising SoC capability and offering
similar IP, you could expect has more insight. But "if it ain't
broke (or nobody says it's broke), don't look at it let alone
fix it" is what happens when a foundry is focused on issues
other than yours.