There will always be the G-D coupling of clocks into analog
nodes. Hard switching is worst. Current-steering can be a lot
lower clock-noise input-output bleed-over. But at 3GHz you
may need all the gate drive you can get. Question is where
reducing gate drive stops reducing settling time, or adds
some other error (like, switch no longer looks like a switch
but more of a resistor with variabilities).
A current source DAC where the "switch" is a diff pair that
steers current away or to the summing node, the gate on
the "to" side is static and the control side only swings just
enough to fully steer current, may be the least clock noise
injection.