DAC design questions (and doubts)

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mruzzi23

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Dear forum users,

For an exam about mixed state circuits, I have to design a 12 bit DAC in Virtuoso with some requirements:

1) 5 output channels
2) Vdd = 1.8V
3) SPI as interface (with 20 MHz clock), which can be made as a testbench
4) update rate (per channel) of 1KS/s
5) Settling time (1%) of analog out = 1us, with capacitive load of 10uF
6) Area < 0.05mm^2
7) Power consumption < 20 uW
8) Noise (in the DC-10KHz band) < 5uV (rms)

I already did the digital part with the SPI testbench (50 ns clock) which outputs a 16 bit serial string, with bits [15:13] which identify the output channel and bits [11:0] identifying the value (bit 12 is unused).
The serial string enters a shift register which shifts the string and creates a parallel string which is in turn given to a demux with 5 outputs that sends to the right channel the 12bit value.

This is my first time designing something like this so the level of complexity for me is a bit high.

My question is: are the the given specs enough for the dac output dual stage miller opamp design? Looks to me that I only have CL, ts, P and NSD specs, but I don't have any Gain, SR, GBW, GM and PM requirements, but again, I'm a novice in this field so I could be wrong.

Also, how can I satisfy the update rate requirement?

Thanks in advance.
 

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You have enough information, more or less. There are certain things not specified, like linearity or type of converter, etc. Question might be more if the specification makes sense. Since this is an exam project, I suppose that formulating a specification is a part of the task. You have to shortlist a few and judge if they can meet the specification and then start massaging it into a block description.

Some hints/comments/questions to guide you, but as indicated - you will have to do a bit of home work
  • Why do you need a two-stage miller-compensated opamp if you have such a large capacitive load?
  • What kind of DAC topology do you envision?
  • The gain is given by the required 12-bit resolution. To meet a 4096-level accuracy, your gain has to be at least higher than that (give-or-take).
  • The 1-% settling error within 1 us gives you the bandwidth and phase-margin requirements. Yet again, with the 10-us load you might not have to care that much about phase margin and can assume a single-pole system. A standard e^(t w0) calculation will suffice to give you the required pole location.
  • Slew rate would be given by current (power) over load capacitance and dictated by the 1-% requirement too. But assuming you need to toggle full swing in 1us would require you to output an SR at 0.99*Vdd/1us = Iout / 10 uF => Iout > 18 A (which is huge!) per opamp. So that puts another requirement on your architecture. (One specific architecture does not suffer from slew-rate limitations). Or your specification is wrong/incomplete. There is for example not clear to me why they specify in us when your sample rate is in ms.
Some juggling like that is required to start to understand the specification.
 

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Dear jjx,

Thanks for your reply, I'll try to answer to everything. I forgot to specify that the project is given from a company, reviewed by the professor and then sent to us. For this project in particular, the application would be the use of the DAC in implantable devices used for the monitoring of bio-electric signals from the brain and for the electrical stimulation of the CNS.

jjx said:
Why do you need a two-stage miller-compensated opamp if you have such a large capacitive load?
Click to expand...
The only architectures that our professor taught us to design are OTA, CS stage and then Miller Opamp, so I thought that opamp was the right choice. Is there another kind of amplifier that should be used with large cap loads?

jjx said:
What kind of DAC topology do you envision?
Click to expand...
I was thinking of using a simple R-2R ladder made with resistors. The other choice would be the other topology that we saw that was the charge redistribution, but the problem is that I don't know how to design it and how to make it work, since we didn't do any design for it and I can't find good sources on how to learn to do it (neither books nor online)

jjx said:
The gain is given by the required 12-bit resolution. To meet a 4096-level accuracy, your gain has to be at least higher than that (give-or-take).
Click to expand...
Oh, I think I understood. So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right?
Thanks for that tip, I'll take a look at it!

And that much of a current (that's really high) is strange for an application like the one I described before, right?
Ok, so there's also a possibility that the specs are not complete. I wanted to ask about that to my professor but he's not famous for being available that's why I'm trying to look as much as I can around the internet.

Thanks again
 

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mruzzi23 said:
I was thinking of using a simple R-2R ladder made with resistors.
Click to expand...
Perhaps you're already aware of all-in-one DAC chips available to convert given amounts of bits. 12-bits normal cost higher than $10. And the experimental stage may consume several chips.
 

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  • "... and for the electrical stimulation of the CNS ..."
    • Ok, so either your DACs are for stimulation or for reference to the ADCs. Nevertheless, 10 uF sounds large in both cases...
    • And it might also be that they have an idea of what they need in an electrical way, but not fully sure of how it is implemented.
    • And yes, that will fry the nerves quite well and give seizure.
    • Here again, remember that response time of the cns is in the order of ms. µs does not make much sense tbh.
  • " ... Is there another kind of amplifier that should be used with large cap loads? "
    • Miller-compensated opamps are used to move the dominant pole inside the OTA and typically used for low(ish) capacitive loads (unless you add an additional source follower inbetween). Folded cascode would do in your case, I would guess. Beware of resistive load in the electrodes to the nerves.
  • " ... using a simple R-2R ladder made with resistors ... "
    • R-2R is dead simple to design, so probably an OK choice with the output buffer. You can drive it with current sources and also scale currents to obtain thermometer coding (in case you would have had a linearity requirement on your DAC).
    • A so called current-steering DAC does not need a buffer nor suffer from slew rate. But has limited swing and requires resistive termination (for your case).
  • "... So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right ..."
    • Yes. The closed-loop accuracy of the opamp would be 1/(1+1/A). A caveat here is once again that they have not specified DAC linearity and thus requirement might not be that strict to resolute the whole DAC range properly
  • my professor but he's not famous for being available that's
    • Haha That's a very common phenomena among professors
 

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Dear jjx,

First of all, happy holidays!
I had the chance to have a meeting with my professor, he told me that the specs are not wrong, he said that everything looks ok to him. But, I still have doubts.
I started to do some calculations and, as you said, the situation looks strange.

I'll start from the SR spec. We know that SR is equal to ΔV/Δt and also Iout/CL (page 4 of https://ww1.microchip.com/downloads/en/appnotes/00884a.pdf).
Keeping in mind that the opamp would never give me full swing, I suppose I'll have 1.6V (10% of the full swing value) as my ΔV and I know that my Δt is 1us.
I have a request on the power and so Iout will be P/V=20uW/1,8=10uA (approximately).

So SR in the first case is 1.6 V/us, while in the second case I have a SR of 1 V/s. Those specs are not converging to a common point, and that's driving me crazy.

To have a SR of 1.6 V/us, the calculations say that there should be a current of about ~16A and so a P of 28,5W: that seems really really high to me and still makes no sense, especially for this kind of application.

As for the PM, he said that 60º is the standard, so I have to use that spec.

He confirmed the gain spec tho.

And last thing he said, don't worry about the area request.
 

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Hi everyone! I think I finally solved (almost) all the specs doubts, if someone can give me confirmation it would be really helpful my digital part of the project is ready and working, so now it's only a matter of designing the opamp in the correct way.

Looking at the specs, for the amp I should take into account these:

• update rate (per channel) of 1KS/s:

the output of the overall DAC is limited by this spec, even if my digital module can go faster than this (and it can, since it supports frequencies up to 200MHz), it will always be limited by the requested analog output frequency/update rate.
An update rate of 1KS/s means a sample every 1ms. Considering a single pole system, my DAC will reach its full output voltage after 5τ, which is the time constant of my system.
Putting into relation the 5 tau and the update rate of a sample for every second, it is clear that 5 tau is equal to 1 ms; so, my tau will be equal to (1/5)ms=0.2ms. From the τ value, I can first find the omega as 1/τ and multiplying by 2pi, the cutoff frequency (and so the BW of my opamp), which will be equal to ~32kHz.

Since my DAC needs to have a 12bit resolution, my Ao spec is 4096=~72dB.

From these two specs, I can find the GBW of the amp, which should be 4096*32KHz = 130 MHz

• Settling time (1%) of analog out = 1us, with capacitive load of 10uF

The settling time gives me the SR spec -> 0.99*Vmax/1us, my Vmax will be around 1.6V so the SR has to be about 1.6x10e6
As for the capacitive load, our professor said try to design the opamp for a load as big as you can, because for a 10uF cap he said a multistage+buffer (maybe a CD stage) configuration would be right way to do it.

So, since we are considering a smaller cap, I'll use a two stage compensated Miller amp, which should be ok for these new specs.

• Vdd = 1.8V and Power consumption < 20 uW

These two specs give me the I_tot for the opamp, which will be ~11uA

• Noise (in the DC-10KHz band) < 5uV (rms)
The noise spec is still unclear to me, why should you integrate it in the DC-10KHz band? What design parameters can you extract from this specification?

Thanks in advance.
 

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mruzzi23 said:
Considering a single pole system, my DAC will reach its full output voltage after 5τ, which is the time constant of my system.
Click to expand...
No.
1) The DAC output will be fast
2) the filter output will be delayed
3) tau is "The time constant"! How can 5 tau be "the time constant of your system"? What does this mean?

Settling time: there always will be an error. You have to define the "allowed" error first to calculate how many tau this takes.
as a rule of thumb:
1tau --> 30%
2tau --> 10%
3tau --> 3%
4tau --> 1%
5tau --> 0.3%
6tau --> 0.1%

Maybe you want your tau to be 0.2ms. (Did not check whether this makes sense). Then this has nothing to do with "1 sample per second". It will be 0.2s independent of sampling rate.
fc = 1/(2 * Pi * tau) .. then fc = 788Hz.
In either case 788Hz as well as 32kHz violates nyquist. As long as you are aware of this .. everything is fine.

No, the bandwidth of you OPAMP is high (and should be), the bandwidth of the filter is 788Hz or 32kHz.

mruzzi23 said:
• Settling time (1%) of analog out = 1us, with capacitive load of 10uF
Click to expand...
Where does the 1us come from? Why 10uF load? This is a huge load and ususlly can´t be driven to get a settling time of 1us.
--> makes no sense to me.

Klaus
 

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    mruzzi23

    Points: 2
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Dear Klaus,

First of all, thanks for your reply. I'll start from the last question.
KlausST said:
Where does the 1us come from? Why 10uF load? This is a huge load and ususlly can´t be driven to get a settling time of 1us.
Click to expand...
The value of 1us is given from the specs that the company gave to us. The text that gave to us says:

Design a multichannel 12 bit DAC with the following specs:

1) 5 output channels
2) Vdd = 1.8V
3) SPI as interface (with 20 MHz clock), which can be made as a testbench
4) update rate (per channel) of 1KS/s
5) Settling time (1%) of analog out = 1us, with capacitive load of 10uF
6) Area < 0.05mm^2
7) Power consumption < 20 uW
8) Noise (in the DC-10KHz band) < 5uV (rms)

And I agree, 10uF is really an high value for a load, so I talked about that with the professor and he said no problem, use a load value of your choice and so I decided to stay around the 1-10pF range (maybe less).

KlausST said:
No, the bandwidth of you OPAMP is high (and should be), the bandwidth of the filter is 788Hz or 32kHz.
Click to expand...

When you talk about the filter, are you talking about the filter behaviour of the opamp? Because there's no filter involved in this project, I should only use the R-2R ladder and design an opamp (and use it in an inverting configuration) which will be at the output of the ladder.

Oh ok, now I understand. But now the question is, how can I derive the other design parameters from the specs they gave to me? I really have no idea now, I thought that considering the 1Ksample/s spec was the right way, but now I'm confused.
I know the Ao spec (given by the resolution), the SR (given by the settling time), but I have no idea about the GBW (and how to derive it).

Another thing that's not clear to me is: how are the two freqeuency values violating Nyquist sampling theorem?

Ok and after selecting the allowed error, how can you derive a design parameter from it?

Thanks for your help, Klaus.
Analog design is to me is as interesting as it is hard to understand it fully. And I really want to be good at it.
 

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Not I did talk about a filter and an OPAMP. I just referred to your informations.
"...the cutoff frequency (and so the BW of my opamp), which will be equal to ~32kHz."
--> "Cutoff frequency" clearly describes a filter. also: "single pole", "time constant", "tau"

mruzzi23 said:
Another thing that's not clear to me is: how are the two freqeuency values violating Nyquist sampling theorem?
Click to expand...
Nyquist says that you need more than twice the sampling frequency than the analog frequency of interest.
Thus 1ksmpl/s results in less than 500Hz analog frequency.

If you violate it just means you get overtones, switching noise, and you can´t get a clean waveform reconstruction.
Again: if you aware of it - and fine with it - there is no problem.

From my experience: (more than 2 decades of professinal indusrial equippment develeopment)
* I never had the requirement for 1us settling time with a 1ksmpl/s sampling rate. There might be applications for this .. but for the kajority of applications it makes not much sense.
The other way round: using an ADC in "undersampling" technique (which also violates nyquist) i sued quite reguralely. But still you need to know what happens - especially that you get "alias frequencies".

mruzzi23 said:
Ok and after selecting the allowed error, how can you derive a design parameter from it?
Click to expand...
The task is not clear to me.
Where does your tau, 5 tau, ans 0.2ms come from? Ist it you or the requirement.

When I see a "settling time of 1us to 1%" then for me it means:
1% error --> 4 tau. 4 tau = 1us. 1 tau = 250ns.

I don´t see any reference to the 1ksmpl/s here. It could be 10 smpl/s or 10k smpl/s and still tau is 250ns.

I did not participate your class, so I don´t know what and how you learned.


Klaus
 

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Dear Klaus,


Alright, clear. But isn't the opamp I have to design, in this particular case, acting like a single pole system?
And so, because of that, it'll have the frequency beahviour of an LPF, which means that it'll have a cutoff (or corner or -3dB) frequency in correspondition of the said pole. I know that's just a way to simplify things and calculations.
Am I considering everything in the wrong way?

Right, this ensure that the converted signal will be a good copy of the original one.
But how does one use the update/sample rate and analog frequency as a useful info to put it into the opamp design?

As for the last part, unfortunately I don't really know what the future usage of this project will be, I just know that the company works in the biomedical sensing devices field (this project is linked to some sort of conversion from data coming from nerve sensing).


- 5 tau comes from the 99% settling time requirement: 5% error is 3 tau, 2% error is 4 tau, and so 1% error is equal to 5 tau.
- the fact that 0.2ms (or 200ns) came out was because of a wrong computation, I was linking the tau to the sample rate value, which doesn't look like the right thing to do

Ok, clear, so tau derives from the settling time relationship with the time constant value and for 1% error in 1us it is equal to 200ns.

But now that I know my time constant, how can I put into account for example the Update Rate spec and derive some design parameters?
More specifically, how can one derive a design parameter like the GBW from all these relations?

All this technical aspect of the design will give me a mental breakdown really soon, I can see it
 

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mruzzi23 said:
Alright, clear. But isn't the opamp I have to design, in this particular case, acting like a single pole system?
Click to expand...
Yes, it is at least a 1 pole system.
But usually not that "adjustable" one with a cutoff of 788Hz or 32kHz.

I differ between
* a bare OPAMP (it´s cutoff usually is in the low Hz.. while having high gian)
* a OPAMP_circuit (used to amplify and not as a dedicated filter) it´s cutoff is due to it´s feedback much higher (while the gain is much lower)
* an OPAMP filter circuit (here external parts are used to determine the cutoff frequency)

Now when you say "OPAMP" which one of the above do you mean?

mruzzi23 said:
Am I considering everything in the wrong way?
Click to expand...
No, in no way. I think you are doing a good job.
And it´s quite normal to have a different view as a student than an enigneer with decades of experience. Nothing wrong with the one or the other.

****

1 tau = 36.8%, 2 tau = 13.5%, 3 tau = 4.98%, 4 tau = 1.83%, 5 tau = 0.67% .. so your values are closer than my "over the thumb".

****
mruzzi23 said:
But how does one use the update/sample rate and analog frequency as a useful info to put it into the opamp design?
Click to expand...
Honestly: I don´t see that the one depends on each the other ... in your case, since it is overruled by the 1us settling time.
It maybe more relates to the digital interface ...


Hopfully others contribute to give you more assistance.

Klaus
 

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I was referring to the OPAMP circuit, but you are right, the "OPAMP" word describes just the bare OPAMP.
Thanks for claryfing it, technical language is important and I'll definitely put more attention on it and use the word in the right way in the future

Yes, it is right, same topic but different views thank you for your support
KlausST said:
Honestly: I don´t see that the one depends on each the other ... in your case, since it is overruled by the 1us settling time.
It maybe more relates to the digital interface ...


Hopfully others contribute to give you more assistance.

Klaus
Click to expand...

Yeah, can be, I'll investigate the topic a little bit more with my professor.

Thanks for your time and for your help Klaus, have a nice day!
 
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One of these specs is in error as they are conflicting.

5) Settling time (1%) of analog out = 1us, with capacitive load of 10uF
7) Power consumption < 20 uW

The sensible answer is, it's a typo error for 10 pF load which may be typical for some analog devices.
Using a 1.8V CMOS Rail-2-Rail Op Amp with a BW > 20 MHz with low Vio ought to be sufficient and easy to specify but the operating current is very low so this is not an ordinary OA so it cannot drive much current.

- it turns out from looking at search tables that there is a supply current uA*MHz product limit and this requirement might be trimmed down to 0.5 MHz 10 uA 1.8V or 5 AHz So a current-BW budget must be worked out. https://www.digikey.ca/en/products/detail/stmicroelectronics/TSV6191AICT/2650947
 
Last edited:

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Good morning everyone!
The project is finally finished. In the end I decided to design everything for a 1pF load capacitance and to use a two stage miller opamp.
The DAC is working and the Professor said that it was good anyway, even if not all the specs were satisfied.
Many thanks to everyone for the help.
 
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