Prashanthanilm
Full Member level 5
Hi all,
Please can anyone tell how to design D-latch with clock and async clear.
The problem here is the output from aync clear should always be given to feedback to function properly.
Thank you
Please can anyone tell how to design D-latch with clock and async clear.
The problem here is the output from aync clear should always be given to feedback to function properly.
Thank you