D flip-flop

[TXRX]

Hi,

I want to memorize the state of a switch, see attached schema, i connect DFF from ON-SEMI pn:NL17SZ175DBVT1G to the switch, the D input will move to Q output at rising-edge of CONTROL signal CP, i dicide also to connect /C input to CONTROL input in order to insure the Q=0 when CONTROL=0.

Is it must to do time delay the CP input AFTER /C input like the graph at page 6 on attached data sheet ? , I connect both of them to CONTROL signal in order to save components for delay circuit.

 

[KlausST]

Hi,

Is it must to do time delay the CP input AFTER /C input like the graph at page 6 on attached data sheet

Don´t look at a graph. They usually are not to scale.
Look into the timing specification "AC ELECTRICAL CHARACTERISTICS"
--> trec = Recovery Time, /C to CP

I don´t know whether this gives the expected "memorize" function.

Did you check `373 Latch function?

Klaus

 

[TXRX]

'373 Latch is Octal and big IC i need only 1 DFF.

--- Updated Apr 19, 2022 ---

The Recovery Time: /C to CP for pn:NL17SZ175DBVT1G acc. the data sheet is minimum 1nSec over temperature, So it is look that i need to add RC circuit at CP Input.

 

[KlausST]

Hi,

as with ´175 there are multiple and single ones in a package.

Klaus

 

[TXRX]

'373 Latch is Octal and big IC i need only 1 DFF.

--- Updated Apr 19, 2022 ---

The Recovery Time: /C to CP for pn:NL17SZ175DBVT1G acc. the data sheet is minimum 1nSec over temperature, So it is look that i need to add RC circuit at CP Input.

I add resistor of 20K to CP Input (The Capacitance is 2.5pF) so it will give Recovery Time of around 34nSec.