Jun 30, 2016 #1 A Ashish Agrawal Member level 3 Joined Mar 24, 2015 Messages 60 Helped 8 Reputation 16 Reaction score 8 Trophy points 8 Activity points 502 Hi All, I have attached a figure. Can this architecture be used as D flip-flop (edge triggered) provided delay of inverter is very less? if Yes, then why don't we use it, as it will take less area? Regards, Ashish PS : Please ignore this post. It's wrongly posted. Last edited by a moderator: Jun 30, 2016
Hi All, I have attached a figure. Can this architecture be used as D flip-flop (edge triggered) provided delay of inverter is very less? if Yes, then why don't we use it, as it will take less area? Regards, Ashish PS : Please ignore this post. It's wrongly posted.