D-Flip Flop pos-edge triggered, lo-async-clear/set, q-only

Status
Not open for further replies.
U

urimi

Junior Member level 1
Joined
Mar 23, 2013
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Visit site
Activity points
1,385
Hi friends,

how to design a d flip flop with positive egde triggered, low asyncronous clear and set and q only using cmos, could you please give the suggesions for implementation.

thank you in advance,

Regards,
urimi
 

Attachments

  • Screenshot at 2013-11-05 10:52:34.png
    180.2 KB · Views: 148

Hi,

There is many topologies are available for FF ..
In simple, Two latches are combined to give you a FF of your choice...
Refer "CMOS circuit Design, layout and simulation" by JAcob Baker or search the net..

Thanks,...
 
Reactions: urimi

    U

    urimi

    Points: 2
    Helpful Answer Positive Rating
An old RCA CMOS databook is a handy friend to have.
Back when real men published their schematics without
fear or greed.
 
Reactions: urimi

    U

    urimi

    Points: 2
    Helpful Answer Positive Rating
Yes many topologies are avalable.
but my target is to reduse the power comsumption.

Thank you,..

- - - Updated - - -

Thank you friend,........
 

Thank you............erikl

due to this area is more ........i have to reduce the area also for high speed.

Regards,
urimi
 
Last edited:

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…