D flip flop metastability

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Ahmed_elshaer

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Can a D flip-flop go metastable if the minimum clock pulse requirement is violated even if the inputs are stable?
 

crutschow said:
Yes.
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Could you please explain why?
my understanding is that metastability only happens when the FF is expected to change It's state (from 1 to 0 or vise versa) and a timing violation happens which will cause metastability for sometime.
Hence, if the input is stable, there will be no change in the state.
Do, if the clk pulse is less than the min, how/why can the D FF go metastable at this case?
 
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I doubt that the question can be answered without referring to the internal circuit. For the usual CMOS master-slave design with transfer gates, I don't expect metastability.
 

Hi,

You wrote: "if the inputs are stable".

But now I guess you meant: " when the input = DFF_out".

Klaus
 

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