D-flip flop based on transmission gates and NAND2 gates

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serhannn

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I want to design a master-slave type D Flip-Flop using NAND2 (two-input) gates and transmission gates with asynchronous Set and Reset. I found out how to do it using NAND3 gates, but I don't have the schematic for NAND2 gates. Can anyone give a link to that or upload the schematic? Also, different kinds of D Flip-Flop topologies are appreciated.

Thank you very much.
 

Three input NAND gate using 2 input NAND gates.

**broken link removed**
 

Its very easy............design an ordinary D flip flop using transmission gates and inverters.........at the output 'q' terminal place one NAND2 gate with one input as the 'q' terminal of the flip flop and the other as 'Presetbar' this ll implement active low asynchronous preset input based D flip flop........with a similar logic reset also can be included........hope this helps.........
 
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