cyr
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m4k ram
I'm trying to implement a simple instruction cache for a small CPU, inside an Altera Cyclone FPGA. I'm using M4K blockrams in "simple dual-port" mode, with separate read and write clocks (actually the same clock, but separate clock enables). The read port is connected to the CPU and the write port connected to the external bus. I *dont* use registers on the data outputs.
When there is a cache miss I want to stall the CPU pipeline, including the read side of the block ram (I need to save the current adress) - so I use my "cache hit" signal as a clock enable. The problem is that after the new data and tag has been written into the rams, the old data still remains on the output side. Like I said, I *dont* have any output registers so I expected the new data to flow right through, but nothing new comes out until I force the clock enable for the read port high.
Am I being stupid, or is there a bug in the simulation models, or does the M4K block RAM really behave like this?
I'm trying to implement a simple instruction cache for a small CPU, inside an Altera Cyclone FPGA. I'm using M4K blockrams in "simple dual-port" mode, with separate read and write clocks (actually the same clock, but separate clock enables). The read port is connected to the CPU and the write port connected to the external bus. I *dont* use registers on the data outputs.
When there is a cache miss I want to stall the CPU pipeline, including the read side of the block ram (I need to save the current adress) - so I use my "cache hit" signal as a clock enable. The problem is that after the new data and tag has been written into the rams, the old data still remains on the output side. Like I said, I *dont* have any output registers so I expected the new data to flow right through, but nothing new comes out until I force the clock enable for the read port high.
Am I being stupid, or is there a bug in the simulation models, or does the M4K block RAM really behave like this?
