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To build a cycle-accurate model for a processor architectrure is a non-trivial task. If you are just starting with your proj, you may find an instruction accurate model handy.
It is a few days work. An example is given in an uploaded paper by trader named: "Build your own RISC processor simulator". Some issues are highlighted there.
What is the processor you imply, CISC, RISC, employs delayed branches. All these details add to the complexity of the model.
In the web, cycle-accurate models to start with are more rare than instruction-level models.
do u have any paper, books, or web site can share?
we already have an instruction level model, and it works fine. Our RTL also works fine. But we have a lot of pain debug the RTL, that's why we need a cycle level acurate model before begin next project.
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