Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cutouts in ground plane beneath SMPS switching nodes?

cupoftea

Advanced Member level 6
Advanced Member level 6
Joined
Jun 13, 2021
Messages
3,057
Helped
62
Reputation
124
Reaction score
139
Trophy points
63
Activity points
15,948
Hi,
When you lay out an SMPS, do you have cutouts in the ground plane beneath switching nodes in order to improve common mode EMC?..
.ie, to stop high frequency capacitive currents getting capacitively coupled into the ground plane?

I mean, with 4 layer, 1.6mm PCB, the centre core is usually 1mm thick, and the outer prepregs are 0.25mm thick...this means there is only 0.25mm
separation between top copper and layer 2 copper.

So if the ground plane is on layer 2, then it will be closely capacitively coupled to the top layer, and so will couple very well capacitively
to the top layer...and if that has the switching node on it...then we are talking big capacitive currents!
 
It depends. How is switcher circuit common node related to ground plane? If it sits on common ground, it doesn't cause common mode noise in the first place.

My first doubt are switching currents flowing in and out of the switcher circuit, how are they filtered?

Even if switcher sits on common ground, it may be useful to have a local switcher ground plane, keeping commutating currents (and also capacitive currents) inside the switcher block. In- and output get LC pi filters, capacitors connected to local and common ground respectively.
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top