Current steering DAC,glitch help

[wang.yuanzhuo]

glitch in current steering dac

the circuit cell

Added after 12 minutes:



Added after 11 minutes:

I'm design a DAC used the classic current steering circuit. But I need a large fixed output voltage range.
It cause large step in the common source node of switch M3 and M4 (>300mv), also a large glitch at the bias node vb1. The loading of vb1 is heavy,so it can't recovery quickly and my setting is bad. I've add large cap at the node of vb1 and vb2, but still can't supress the glitch well.
Could any one give me some suggestion to supress the glitch or make the recovery of vb1 quickly?
Thank a lot

 

[wang.yuanzhuo]

Is there anyone help me?
Help!!!!!

 

[rfsystem]

I think that the switch PMOS change form SAT region to LIN region while the output node is rising from 0V to 1V.

If the switch control voltage is low enough (more positive) for M3 it remains in saturation (SAT region) also if the output node rise. Or in another term M3 is then an additional switchable cascode device.

So I think the effect is because of a missdimensioning.

 

[wang.yuanzhuo]

Thanks a lot.
The switch PMOS in LIN region is the biggest problem. Now I'm trying to rise the control voltage.
Thanks for your suggestion