Current Mirror Simulation in Cadence

[muffassir]

Hi all,

I want to simulate simple current mirror.I am using 180gpdk process in cadence. The Iref is 10uA and vdd is set to 1.8V.I know how it works and what will be the output. But i donno know how to simulate it. I am doing trans analysis with stop time of 200ns . W/L is 2u/180n . same for both.







The out put should be -10uA for the above ckt. But i am getting some other wave see the image below.



Please help me with the selecting the values and correct my ckt if needed.

 

[jimito13]

The right transistor (NM0) is not biased at the drain node (VDS=0) as indicated from your plots so no DC current can flow there!
Put an ideal Vdc there with the desired value for NM0's VDS and resimulate.
Alternatively you can put a real load there like a pmos diode transistor that it's dimensions will adjust the VDS at the desired point.

Finally,transient analysis i think has no meaning here since it is a dc circuit.If you want to use this ckt to mirror some signal then you can run a time-based simulation.

 

[muffassir]

@Jimito,

Hi,
Please see the images of modified schematics and the obtained outputs.I think its correct now.

Well i am newbie in analog design as well cadence. Can u please name the anaysis to use that is available in cadence since u said trans analysis have no meaning.do u mean i run dc analysis but i think its not time based.

 

[jimito13]

You are correct now.

Since it is used as a bias DC ckt you must run DC analysis.