[SOLVED] Current mirror noise

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analogonics

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Circuit Scenario:
I have a current subtractor circuit made up of pmos and nmos wide swing current mirrors. The output of the circuit for now is tied to a 0.9 V ideal voltage source to have a proper biasing.
The current difference is seen at the terminals of the voltage source. The current range for the nmos and pmos mirrors is from 0 to 12 μA. The difference can be a maximum of 50 nA.
My overall system works at a max frequency of 32MHz, i.e., the clock frequency.

The circuit works perfectly when I have not turned on the transient noise. (The transient noise Fmax was 1.6GHz, around 50x the max frequency of operation of the overall system). As soon as I turn on the transient noise, the peak-to-peak value of the output current of the two mirrors is on the order of 300 nA. I cannot afford to have this fluctuation above the 1/128 of 50 nA value, i.e., max up to some 100s of pA (Lower, the better), say around 300 pA. This 128 factor is because the current after the subtraction has to be scaled by a factor of 128. So, if even 1nA of error in the subtraction gives a huge error at the output of the scaling. For now, I have a CCCS mirroring the subtracted current from the 0.9 voltage source and multiplied by 128 factors. I need some ideas as to how to tackle the noise problem.

I am willing to pay in terms of the mirror's bandwidth by bringing it up to some 20s of MHz or also in terms of area and power.
 

First decide whether you believe the tnoise modeling -> outcome.

Play with sizing up devices until it costs you unacceptably in BW or leakage floor sum gets too close to LSB.
 

First decide whether you believe the tnoise modeling -> outcome.

Play with sizing up devices until it costs you unacceptably in BW or leakage floor sum gets too close to LSB.
All the other blocks of my system is ideal. Only the mirror in the subtractor is real. I wanted to see the effect of the noise in those mirrors on the overall system.
When only the subtractor is simulated, I.e., just two current mirrors with similar DC inputs and a bit of offset just to see the subtraction operation. The noise peak to peak at the output of subtractor is reduced to 10s of nA only when I keep a series Resistor of the order of 1Mohm.

This gives me a direction that the next circuit that picks up this subtracted current needs to have a very high input impedence say an opamp. Do you think it is a good thought process. Or do you have any suggestions.?
 

Is the high value resistor simply low-pass-filtering (w/ Cin_next) the noise for you?

Might look at what's "provoked noise" (like clock feed through) and what is "generated noise" (from device noise sources)?
 

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