Not too bad - but a nightmare for routing the layout. Hope this is a DC circuit, so routing symmetry isn't compulsory.
However: do you really need this 3:15 configuration? Wouldn't a 1:5 (or an even-numbered 2:10 , which is much easier to achieve regarding common centroid) configuration also be sufficient for your small-mismatch requirement?
In any case you need dummies around the whole array to guarantee a continuous environment also for the border devices, otherwise even a darned good common centroid symmetry would be useless.
On the contrary: at least in Southern Germany (didn't you live there some time ago?) this rather means a good praise. If you say about a girl "she is not too ugly" this would mean she is rather good looking, a pretty girl. ;-)... you are saying not too bad...... it mean bad
I thinkhow could you match three transistor (A, B, C)with m=1 ????
DDDADD
EEBEEE
FFFCFFOn the contrary: at least in Southern Germany (didn't you live there some time ago?) this rather means a good praise. If you say about a girl "she is not too ugly" this would mean she is rather good looking, a pretty girl. ;-)
I think
... with dummies all around would be good enough. Not really common centroid, but saves a lot of Si real estate, and is much easier to be routed.Code:DDDADD EEBEEE FFFCFF
Would be interesting to compare MC mismatch (+ process) results of m=1, 2, and 3 layouts!
Sure, but this could create the same mismatch inaccuracies!... one can mirror the current to another mirror then recover it back again with another mirror
No paper on this, sorry. But it's simple: the routing parasitics (for CMOS mainly the capacitive ones) contribute to the actual nodes' caps (output + input(s) caps), and by this can create different fan-out loads and - so - delays.... do you have any article about the effect of the non symmetry of the routing in general
Thank you very much erikl,
see you ;-)
... non-symmetry routing... it leads to non uniform developed stress in the chip which degrade the reliability
Where did you hide it? ;-)Kindly refer to this paper, here is something about the stress
If you are not routing over the active area but over thick oxide, you're not routing over transistors! And then it shouldn't affect the transistor mismatch, of course.1. does the routing over the transistors (except the gate area which is not recommended to route over it) contribute to the transistors mismatch ???
... I am thinking that since the routing is not in the active area where the transistors are, and because it isolated from the transistors with a thick oxide then it will not effect the matching
Sure, why not?2. is it possible to use the metal 3 for any routing ???
I've got no access to IEEE papers any more, sorry. Non-uniform metal coverage of course may create stress on silicon, but primarily has nothing in common with non-uniform routing lengths.**broken link removed**
May be, depending on available number of metal layers, but then not necessarily limited to power supply routing.for metal 3 question I dont remember where I read it used only for VDD and ground connections
Thank you. But still:take it, it is available for free in google
Non-uniform metal coverage of course may create stress on silicon, but primarily has nothing in common with non-uniform routing lengths.
I don't know for sure, but I'd think your teacher means the cost of the layout, which includes both the effort to create and verify it, and the cost of parasitics and silicon area - all this seen in terms of achieved mismatch reduction in comparison to the simplest execution (1:5 in your case).what is the floorplanning function ???
Thank you. But still:
I don't know for sure, but I'd think your teacher means the cost of the layout, which includes both the effort to create and verify it, and the cost of parasitics and silicon area - all this seen in terms of achieved mismatch reduction in comparison to the simplest execution (1:5 in your case).
Or, it could simply mean: "Don't exaggerate!" (no harm meant).
Where did you hide it? ;-)
If you are not routing over the active area but over thick oxide, you're not routing over transistors! And then it shouldn't affect the transistor mismatch, of course.
Sure, why not?
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