current mirror matching with different size transistors

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Junus2012

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hello analog guys

I need to have a simple current mirror with four branches (A,B,C,D), the current in D and C are equal and it is twice the currents in A and B. so basically C and D transistor are double size of A and B.

I would like to do the layout of this mirror so kindly suggest me a good fingering array to match them. my idea is to have A and B with m=4 and C,D with m=8. what about your ideas and how it will be the array ???

Thank you in advance
looking forward for your kind reply
 

Junus2012 said:
I would like to do the layout of this mirror so kindly suggest me a good fingering array to match them. my idea is to have A and B with m=4 and C,D with m=8. what about your ideas and how it will be the array ???
Click to expand...

Hi again Junus,

fingering (f) isn't so good for matching as multiplicity (m) is, i.e. usage of multiple single identical transistors with f=1, but I guess that's what you're thinking of, anyway.

Of course you can spend 24 identical transistors if you like and are able to afford the necessary layout area, but I don't think the matching will be much better than e.g. a Dummy-A-C-D-D-C-B-Dummy row with just 6 transistors + 2 dummies.
 
hello erikl

i was sure to see you in this post

yes exactly as you said, i mean to see multiplying.

Kindly can you give your suggested array in two diamentions that include all the transistors please

 

Junus2012 said:
... can you give your suggested array in two dimensions that include all the transistors please
Click to expand...

If you absolutely insist: There are many possibilities, but with regard to common centroid design, I'd suggest the following array:
Code: 
ADC or CAD
CDB    DBC

4 dummies at the sides are necessary, none at top & bottom (like single row), because all transistors see the same environment at top & bottom. Horizontal W transistors need only min. W dummies (this is enough to maintain a good side environment), so layout area can be saved.

S to D always in the same direction (same current flow direction for all transistors, i.e. no mirror symmetry in this respect). Needs more routing, and so adds more parasitic capacitance. But I guess it's a DC application anyway?

Horizontal and vertical directions may be exchanged, of course. Even later so, when you instance it as a block, up to your aspect requirements.
 
many thanks erikl , you are my layout supervisor

see you next

- - - Updated - - -

Please Erikl correct my suggestion if it is wrong

for better matching I am assuming that A and B with m=2 and C,D with m=4 and these are my array

C D D C
A B B A
C D D C

or take this with x dummy

C D D C
X A B X
X B A X
C D D C

Also please I would ask you what about if our mirror factor is Fractional numbers, like 1.3 or 1.2 and so one, how then we make the array for this if the transistor sizes should be equal as recommended ???
 

In such cases, you'd need dummies all around the array, because otherwise also the top & bottom rows would see a different environment as the middle row(s). So for ≧ 3 rows, the dummy requirement will get excessive in comparison to the number of useful array devices (14:12 for your first array above, 1:1 for the lower one). I think this is only reasonable if (number of dummies) « (number of used devices), i.e. 2(x+y) « xy . But it's also a question of available silicon area, of course.

Junus2012 said:
Also please I would ask you what about if our mirror factor is Fractional numbers, like 1.3 or 1.2 and so one, how then we make the array for this if the transistor sizes should be equal as recommended ???
Click to expand...

In this case, I'd actually use 13 resp. 12 devices of 0.1 .
 

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