Re: Current Carrying Capabilities of PMOS & NMOS and Ideal Load for Current-Mode Circ
You're asking questions which seem to not relate to
anything.
My questions are very straightforward. I'm asking 2 questions-
1) We know that PMOS acts as good pull-up device & NMOS acts as good pull-down device. Hence we use CMOS. Generally a capacitor is connected as a load to such CMOS circuit. We measure the charging & discharging times of the transistor, which we wish to be same. The PMOS charges the capacitor to Vdd & NMOS discharges it to Vss. We say that PMOS gives GOOD 1 but POOR 0 & NMOS gives GOOD 0 but POOR 1. This explains the "voltage carrying capabilities" of PMOS & NMOS.
I want to know about "current carrying capabilities" of PMOS & NMOS. For example, consider a single PMOS. If Vss is applied to its Gate, it will be ON & pass the current from source to drain (say Isdpon) through it. If Vdd is applied to its Gate, it will be OFF & will not pass any current or will pass very small current (say Isdpoff) through it. Similar cases for NMOS will give the drain to source currents Idsnon & Idsnoff.
My question is, out of Isdpon & Idsnon, which is maximum? Similarly, out of Isdpff & Idsnoff, which is minimum? And Why..??
2) For voltage-mode circuits, generally a capacitor is connected as a load during simulation. If charging & discharging times of capacitor are same, we consider that our circuit is good. Hence we can term a capacitor as a "suitable" load for voltage-mode circuits.
Is there any such "suitable" load for current-mode circuits? Various options can be Inductor, Resistor, Current Mirror, Current Sink Circuit, etc.
I can surely claim that a larger current-mode circuit can not run properly without a load connected at its output and sometimes output current varies with the load, making the output less reliable.
I also want to know about some good circuits for CCVS, VCCS & CCCS working properly at 90nm technology.