It is mainly
Accurate Active Device models for RFIC process...
Interconnect Parasitic Extractin....
and Single EDA tool for complete RFIC design flow (Schematic to GDS)...
One EDA company is doing good in this domain is AWR see below...
I mean the state-of-the-art designs. I work in research
and would like to know your opinions about main problems
of RFIC designer. Which part of design process takes you
the longest time, what you would like to speed-up, etc.