devaVLSI
Newbie level 5
I am trying to understand the clock building in my design.
How the spec file is generated.
How some of the sink pins are delayed more even there is no latency mentioned in spec file.
how balancing takes place if there is no information regarding balancing in spec file.
How the spec file is generated.
How some of the sink pins are delayed more even there is no latency mentioned in spec file.
how balancing takes place if there is no information regarding balancing in spec file.