robo_kid22
Newbie level 1
- Joined
- Mar 3, 2013
- Messages
- 1
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,298
Hi, so I have been working on a revised design of my first PCB based on the NXP LPC4337JBD144, the first rev is still not programming so while I have been debugging it I have done almost a complete redesign.
Revisions I made from the first design:
- Added bypass caps on all voltage inputs on ever device taking power from any of the power planes (bypass caps were not in the reference design NXP told me to use)
- Added pullups to the JTAG pins
- Added a jumper able pullup pulldown header for the DBGEN and TRST pins for different JTAG modes
- Rerouted the ethernet PHY section to have equal length traces between the PHY and the ARM.
- Changed to a USB micro connector and made the D+ and D- traces equal length.
- cleaned up all the trace routes
I'm particularly looking for feedback on the Ethernet PHY section and the USB section, over all comments on the routing job are welcome. What I have been trying to figure out how to do is do equal length tracing of differential pairs as well as equal length differential pairs with vias as there is no way to route the connections between the ARM and the PHY without Vias no matter what I try, if someone has a suggestion for a better PHY IC that has the same specs as the SMSC LAN8710 but with a better pin configurations I'm open to those suggestions as well. I have attached a smartPDF of my design below. I also want to know what people think of negative space ground planes, the board is 4 layers with a dedicated inner ground plane and power plane, the signals are on the outside. I want to know in what cases one should make the negative space on the outer layers into a ground fill? I'm afraid of getting ground loops but I'm also afraid clock signals could get noisy if there isn't a ground pour around their traces.
**broken link removed**
Revisions I made from the first design:
- Added bypass caps on all voltage inputs on ever device taking power from any of the power planes (bypass caps were not in the reference design NXP told me to use)
- Added pullups to the JTAG pins
- Added a jumper able pullup pulldown header for the DBGEN and TRST pins for different JTAG modes
- Rerouted the ethernet PHY section to have equal length traces between the PHY and the ARM.
- Changed to a USB micro connector and made the D+ and D- traces equal length.
- cleaned up all the trace routes
I'm particularly looking for feedback on the Ethernet PHY section and the USB section, over all comments on the routing job are welcome. What I have been trying to figure out how to do is do equal length tracing of differential pairs as well as equal length differential pairs with vias as there is no way to route the connections between the ARM and the PHY without Vias no matter what I try, if someone has a suggestion for a better PHY IC that has the same specs as the SMSC LAN8710 but with a better pin configurations I'm open to those suggestions as well. I have attached a smartPDF of my design below. I also want to know what people think of negative space ground planes, the board is 4 layers with a dedicated inner ground plane and power plane, the signals are on the outside. I want to know in what cases one should make the negative space on the outer layers into a ground fill? I'm afraid of getting ground loops but I'm also afraid clock signals could get noisy if there isn't a ground pour around their traces.
**broken link removed**
Last edited: