Critical path while using xilinx ise

[Chinmaye]

Dear all,
When i tried to synthesize my verilog code in ISE, my timing report said,

Minimum period: 4.490ns (Maximum Frequency: 222.712MHz)
Minimum input arrival time before clock: 4.358ns
Maximum output required time after clock: 0.728ns
Maximum combinational path delay: No path found

From what i understand, Maximum frequency is determined by the path that takes a longer time to execute. How do i trace that path?

 

[barry]

Your timing report should identify your slowest path.

 

[Chinmaye]

Where do i check that? In the synthesis report right?