[SOLVED] Creating verilog define for filename based on input file path, string concatenation

Code Verilog - [expand]
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`ifdef FILENAME_PATH
  `define FILENAME1 ``FILENAME_PATH/test1.txt     // fail - what does double `` even do?
  `define FILENAME2 {`FILENAME_PATH, /test2.txt} // fail
  `define FILENAME3 {"`FILENAME_PATH`","/test3.txt"} // compiles but gives vsim-pli-3084 ($feof, fscanf etc argument 1 not valid file descriptor)
`else
  `define FILENAME1 /home/hard/coded/path/test1.txt //works, but not flexible for different users.

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module dir_path;
 
parameter string MY_PATH = "/default/path";
 
  string my_str;
 
  assign my_str = {MY_PATH, "/test.txt"};
 
  initial begin
    $display ("start test");
    #10;
    $display ("%s", {MY_PATH, "/test.txt"});
    $display ("%s", my_str);
    #10;
    $display ("end test");
  end
 
endmodule

Code SystemVerilog - [expand]
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module fml;
 
parameter string sim_stimulus_path = "This is my path" ;
parameter string sim_result_path = "This is my path" ;
 
 
  initial begin
    $display("Sim path = %s", sim_stimulus_path);
    $display("Result path = %s", sim_result_path);
    $display("start test");
    #10;
    $display("%s", "`FILENAME_PATH`");
    $display("%s", "`FILENAME_PATH");
    
    #10;
    $finish(2);
end
 
endmodule

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module dir_path_verilog;
 
// parameter [64*8-1:0] MY_PATH; // this results in a string with lots of leading spaces
parameter MY_PATH;
 
  wire [64*8-1:0] my_str;
 
  assign my_str = {MY_PATH, "/test.txt"};     // adds leading spaces due to my_str definition
 
  initial begin
    $display ("start test");
    #10;
    $display ("%s", {MY_PATH, "/test.txt"});  // no leading spaces
    $display ("%s", my_str);                  // leading spaces
    #10;
    $display ("end test");
  end
 
endmodule

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module x #(
parameter sim_path = "string",
...
)(
...
)
 
wire [128*8:0] stim;
assign stim = {sim_path, "/test.txt"}
 
initial begin
  if test==x begin .. end
  `include sample.vh
end
 
.........
`define ORIGIN sim.path.to.module.x
.......
task TSK_OPENSTIM;
  integer data_file;
  begin
     data_file = $fopen(`ORIGIN.stim, "r");
  end
endtask
.....
 
task TSK_READ_FILE
integer scan_file;
//blah
begin
  while (!feof(`ORIGIN.TSK_OPENSTIM.data_file)) begin
 
//magic