cbear81
Newbie level 1
clf file astro
Hi,
I need to generate a two level hierarchical design (chip + block) in Astro. After place and route is complete for the low level block, I need to generate a timing (TIM) view by creating CLF. After setting up the timing I generate the CLF using 'astTimingModel'.
However, I noticed that the input delays are missing from the CLF file. The CLF does contain the output delays (relative to the clock in the form of defineTimeTLU), as well as port capacitance (definePortCapacitance). The lack of input delay information is causing timing violations at the top level.
Am I missing any steps to generate the timing model in Astro?
Also, do I need to use a Hierarchial Timing View (HTV)?
Hi,
I need to generate a two level hierarchical design (chip + block) in Astro. After place and route is complete for the low level block, I need to generate a timing (TIM) view by creating CLF. After setting up the timing I generate the CLF using 'astTimingModel'.
However, I noticed that the input delays are missing from the CLF file. The CLF does contain the output delays (relative to the clock in the form of defineTimeTLU), as well as port capacitance (definePortCapacitance). The lack of input delay information is causing timing violations at the top level.
Am I missing any steps to generate the timing model in Astro?
Also, do I need to use a Hierarchial Timing View (HTV)?