creating schematics in cadence with verilog

statemate_6 · May 22, 2005

hello all,

i'm a beginner in digital circuit design with cadence and want to ask you the following question. i wrote a demultiplexer program in verilog and want to create a schematic in cadence. what should i do? or do you know any links or tutorials explaining that?

thanks

morecode1234567890 · May 22, 2005

i do not know any good toturial, but i think i can help you.

In your CIW, look for Impot. then select verilog, and i think that is all.

I can not give you the information step by step, becouse i have not cadence at home

That is all

Sorry for my english.

good luck with that .... tool

nile_king · May 23, 2005

Hi

just after finish writing ur code and when close if ur code has no error window will appear to u to create block diagram for it
it's very easy

feel_on_on · May 23, 2005

synthetize it with cadence buildgates!ambit

creating schematics in cadence with verilog

statemate_6

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morecode1234567890

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nile_king

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feel_on_on

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creating schematics in cadence with verilog

statemate_6

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morecode1234567890

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