Creating one FSM in VHDL with slow CLK

hello,

I'm designing my first code in VHDL to create one UART.
The principal CLK works at 60MHz, and I need divide the principal CLK for decrease the speed of the UART.
It's normal create one process with one divided clk (signal COUNT(1))? or exist other designs more efficients?


architecture fsm_sencilla of UART_TX is
type estado is (S0,S1,S2,S3,D0,D1,D2); -- 7 states
signal estado_pr, sig_estado: estado; -- Present and future State
signal COUNT: unsigned(7 downto 0):= "00000000"; -- Counter to divide the clk
signal Aint, Bint, Cint: std_logic; -- Save inputs in State S3 ('0' sync)

begin
process(clk, rst) begin
if rst='1' then
COUNT <= "00000000";
elsif (clk'event and clk='1') then
COUNT <= COUNT + 1;
end if;
end process;

process(rst, Aint, Bint, Cint, COUNT(1)) begin
if rst='1' then
estado_pr <= S0; elsif (COUNT(1)'event and COUNT(1)='1') then
estado_pr <= sig_estado;
if estado_pr= S2 then Aint <= A;
Bint <= B;
Cint <= C;
end if;
end if;
end process;

This is good enough for this speed.

you should not divide a clock this way. You should generate a clock enable instead.

Both are same. I do not see any issue Only power will differ.

TrickyDicky said:

you should not divide a clock this way. You should generate a clock enable instead.

Click to expand...

Hello!

thank you both!!
How I can generate a clock enable? Because using my code appears some glitches in the serial Output. I can solve them using one clk enable?

Thanks!

mail4idle2 said:

Both are same. I do not see any issue Only power will differ.

Click to expand...

Maybe in an ASIC, but NOT in an FPGA.
A logic driven clock can have all sorts of timing issues and glitches that make the design very vulnrable to temperature. So they are NOT the same.

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kkdelabaca said:

Hello!

thank you both!!
How I can generate a clock enable? Because using my code appears some glitches in the serial Output. I can solve them using one clk enable?

Thanks!

Click to expand...

Very probably. A clock enable is generated very much the same as you have done for the clock, but you just make it high for 1 clock cycle in the sequence: