Allure2009
Newbie level 1
- Joined
- Aug 17, 2010
- Messages
- 1
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Location
- UK
- Activity points
- 1,288
Dear All,
I have created a design in Cadence IC6 using faraday standard cell lib.
I would like to create layout from the schematic with auto rooting.
I gather "Encounter" tools would be one of the solution yet I need first generate a netlist from from my schematic.
I found this tutorial from IC5 but alot naming had change and i just could not complete the setting base on this old tutorial.
**broken link removed**
can anyone provide the tutorial or manual on how to create verilog netlist from schmatic?
Thanks in advance.
Kind regards
H
I have created a design in Cadence IC6 using faraday standard cell lib.
I would like to create layout from the schematic with auto rooting.
I gather "Encounter" tools would be one of the solution yet I need first generate a netlist from from my schematic.
I found this tutorial from IC5 but alot naming had change and i just could not complete the setting base on this old tutorial.
**broken link removed**
can anyone provide the tutorial or manual on how to create verilog netlist from schmatic?
Thanks in advance.
Kind regards
H