created logic net from UPF is not visible in Modelsim (Questasim) Schematics

add schematic -full sim:/tb/TOP
# ShowFullView error1 DebugDB QueryError:
#   error3 = near ")": syntax error

module min(clk, inputValue);
input clk, inputValue;

always @(clk)
begin
   
end
endmodule
//-----------------------------------------------------------
module minout(clk, inputValue);
input clk, inputValue;

always @(clk)
begin
   
end
endmodule

import UPF::*;

module tb;
reg inputValue;
reg clk;
always #8 clk = ~clk;
always #200 inputValue = ~inputValue;

initial
begin
	$dumpfile("vcd_dmp/dmp_tb.vcd"); 
	$dumpvars(0,tb);//read verilog book for more info on system command 
	
	// set the power to the domains, if you don't do that, nothing will work
	supply_on("VDD_port", 0.95);
	supply_on("VSS_port", 0.0);
	clk =0;
	inputValue =1;
end

initial
begin
	#4000
	$dumpoff;
	$stop;
end

//TOP MODULE INSTANTIATION
min MIN(clk, inputValue);
minout MINOUT(clk);
endmodule

set_design_top tb 

##############################
create_power_domain top_PD -elements {MIN MINOUT}

create_supply_port VDD_port -domain top_PD -direction in 
create_supply_net  VDD_net  -domain top_PD
connect_supply_net VDD_net  -ports {VDD_port}

create_supply_port VSS_port -domain top_PD -direction in 
create_supply_net  VSS_net  -domain top_PD
connect_supply_net VSS_net  -ports { VSS_port}

set_domain_supply_net top_PD \
	-primary_power_net VDD_net  \
	-primary_ground_net VSS_net


##############################
set_scope MIN
create_logic_port outputValue_port -direction out 
connect_logic_net inputValue -ports {outputValue_port}

set_scope /
create_logic_net aaa
connect_logic_net aaa -ports {MINOUT/inputValue MIN/outputValue_port}

vlib work
########## Compile the source files.
vlog -64 -O0 -novopt -work work -L mtiPA -f <...>/minimal_example/scripts/compile_rtl.f -coveropt 1 -vopt

########## Optimize the design.
vopt tb -pa_upfversion=2.0 -pa_upf<...>/minimal_example/SRC/out_questa.upf -pa_lib work -pa_enable=nonoptimizedflow+highlight -o top_opt -work work +acc -debugdb -novopt -pa_lib work -pa_all -pa_genrpt=pa+de+nv+u -pa_checks=s+ul+umi+i+r+p+cp+t+upc+npu+ugc +cover +acc=npr+* -coveropt 1 -O0 -pa_all -pa_behavlogfile=<...>/minimal_example/error

########## Simulate the design and view the results.
vsim top_opt -pa -novopt -pa_lib work -debugdb=<...>/minimal_example/test -l rtl.log -wlf rtl.wlf -L mtiPA -pa_highlight -assertdebug -coverage +notimingchecks -donotcollapsepartiallydriven -autoexclusionsdisable=fsm

log -r /*

run -all

<...>/minimal_example/SRC/tb.sv
<...>/minimal_example/SRC/min.v