CRC circuit question

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in the pdf , step 2 mentioned that I need to run crc_serial() code for N times <-- I understand this.

However, in step 4, why The values are one-hot encoded—that is, each of the NIN values has only one bit set. ?
 

promach said:
in the pdf , step 2 mentioned that I need to run crc_serial() code for N times <-- I understand this.

However, in step 4, why The values are one-hot encoded—that is, each of the NIN values has only one bit set. ?
Click to expand...
The one-hot encoding is just the simplest case, but it isn't necessary to generate table 1 + 2 and the equations.
What you need is only the correlation from a flipped input bit to flipped output bits.
When you flip only one Nin/Min input bit, the same output bits will always flip, regardless of the fixed state of the other Nin/Min bits.
Since the output is all zeros when the input is all zeros, the one-hot input encoding is the simplest case. You directly know that an output bit = '1' is a flipped output bit.
 

In step 3, what does it exactly mean by Matrix H1 describes MOUT(next CRC state) as a function of NIN(input data) when MIN= 0 ?
 

promach said:
In step 3, what does it exactly mean by Matrix H1 describes MOUT(next CRC state) as a function of NIN(input data) when MIN= 0 ?
Click to expand...
It means that the matrix shows the relations between flipped Nin bits and flipped output/Mout bits (= which Nin terms to include in the parallel equations). Min = 0 only means that no Min bit is flipped, that happens for the other table/matrix.
 

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    promach

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okay, could you show me how to obtain the first row (Nin[0]) of table 1 (Min = 0) ?

How do you exactly flip Nin[0] to obtain first row ?
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promach said:
okay, could you show me how to obtain the first row (Nin[0]) of table 1 (Min = 0) ?

How do you exactly flip Nin[0] to obtain first row ?
Click to expand...
You clear/reset everything (=the shift register= Min) and execute the serial implementation N times with "0001" as the input data sequence (= Nin[3:0]).
The bits in the shift register (= Mout) are the data for the first row in table 1.
 

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okay, thanks. I know exactly how to reproduce table 1

What about first row (Min[0]) of table 2 (Nin = 0) ?

 

promach said:
okay, thanks. I know exactly how to reproduce table 1

What about first row (Min[0]) of table 2 (Nin = 0) ?
Click to expand...
In the simulator, you initiate the shift register contents (Min) to "00001" and then execute the serial implementation N times with "0000" as the input data sequence (Nin=0)
 

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okay, now I have reproduced table 2 using your advice above.

However, why is table 2 (Nin =0) needed at all to produce parallel CRC equation ?
 

promach said:
okay, now I have reproduced table 2 using your advice above.

However, why is table 2 (Nin =0) needed at all to produce parallel CRC equation ?
Click to expand...
The CRC calculation depends both on previous bits (used to calculate Min) and new bits (Nin).
So both Min and Nin terms are needed in the equations. Table 1 gives the Nin terms and table 2 gives the Min terms.
 

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    promach

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What does it exactly mean by each set bit j in column i ?

 

promach said:
What does it exactly mean by each set bit j in column i ?
Click to expand...
Each row in table 1 and table 2 corresponds to an Nin/Min "input" bit. Each column corresponds to an Mout "output" bit.
A '1' means that the Nin/Min term must be included in the parallel equation for the output bit corresponding to the column.
A '0' means that the Nin/Min term must not be included in the equation.

By "flipping" one input bit at a time you calculate the rows in the matrices/tables.
A complete column (in both tables) defines which Nin/Min terms must be included in the equation for one Mout output bit.
 

Maybe if you could show how to derive the first parallel equation Mout[0] from table 1 and table 2, then it is easier to understand ?

Mout[0] = Min[1] ^ Min[4] ^ Min[0] ^ Min[3]
 

promach said:
Maybe if you could show how to derive the first parallel equation Mout[0] from table 1 and table 2, then it is easier to understand ?

Mout[0] = Min[1] ^ Min[4] ^ Min[0] ^ Min[3]
Click to expand...
I now see that there is a "typo" in the pdf you have linked ( http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf ).
The line you show is incorrect. It should be:

Mout[0] = Min[1] ^ Min[4] ^ Nin[0] ^ Nin[3]

This may have confused you.
They have it correct in the Verilog code in listing 4.

You get the equation for Mout[0] by looking at the corresponding column in table 1 and 2.
In table 1, column Mout[0], you have '1' in the rows for Nin[0] and Nin[3], which means they are included in the equation.
In table 2, column Mout[0], you have '1' in the rows for Min[1] and Min[4], which means they are included in the equation.
 

ok, but why XOR all four bits together to obtain Mout[0] ?
 

promach said:
ok, but why XOR all four bits together to obtain Mout[0] ?
Click to expand...
CRC calculation in 100% XOR operations.
In the serial implementation they happen after each other.
In the parallel implementation you do all of them in one clock cycle.
When the bits move around in the serial implementation, it is possible that one input bit is "involved" more than once for generating an output bit.
Input signals that have been used an even number of times (zero is even) have no effect, so they don't appear in the parallel equation.
Input signals that have been used an odd number of times have the same effect as being XOR-ed once, so they appear in the parallel equation.
 

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    promach

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