[SOLVED] CRC Calculator in VHDL.

[Ironlord]

I have developed the following code to calculate a CRC.

I am passing it a Start signal and a Frame, which is 12-bits of data. The CRC works picking up the message in Nibbles, so as I have 12-bits, I will divide it into 3 Nibbles.
I am trying to simulate this code on ModelSim, but when I put the Start signal from '0' to '1' it fails. I still don't know what am I doing wrong. Somebody could give me a hint?

The problem is on the sentence "tmpCRC<=crcLookup(miNum);"

Thanks in advance.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith;
use ieee.numeric_std.all;

ENTITY getCRC IS
    PORT(
        Start    : in  std_logic;
        Frame    : in  std_logic_vector (11 downto 0);
        Done    : out std_logic;
        CRC    : out std_logic_vector (3 downto 0)
    );
END getCRC;



   
ARCHITECTURE a OF getCRC IS

    --CRC Look-Up Table:
    type  TABLE is array (1 to 16) of std_logic_vector(3 downto 0);
    constant crcLookup     : TABLE := (x"0",x"D",x"7",x"A",x"E",x"3",x"9",x"4",x"1",x"C",x"6",x"B",x"F",x"2",x"8",x"5");

    signal frameTmp    : std_logic_vector (11 downto 0);        --Copy of Frame input into internal signal
    signal index    : integer range 0 to 3 :=0;
    signal j        : integer range 0 to 11 :=11;
    signal status    : std_logic :='0';
    signal miNum    : integer range 1 to 16:=5;
    signal tmpCRC    : std_logic_vector (3 downto 0):="0101";    --Temporal CRC calculation.



begin

    frameTmp <= Frame;

    process(Start)
    begin
        if(Start='1' and status='0')then
            while(index<3)loop
                miNum<=to_integer(unsigned(std_logic_vector(tmpCRC)));
                tmpCRC<=crcLookup(miNum);
                tmpCRC<=(tmpCRC xor frameTmp(j downto j-3)) and x"F";
                if(j>3)then
                    j<=j-4;
                end if;
                index<=index+1;
            end loop;
            status<='1';
            j<=11;
            index<=0;
        end if;
    end process;
   

    --Outputs--
    Done    <= status;
    --CRC     <= tmpCRC;

end a;

 

[KlausST]

Hi,

it fails

Means what?
Is there an error message?
Or how do you decide "it fails"?

Klaus

 

[FvM]

Besides unclear problem report, you should be aware that your VHDL won't do what you apparently expect. The while loop doesn't work because signal assignments are updated at the end of the current simulation cycle, in this case when finishing the process. The code can be possibly rewritten with variables.

Secondly, an iteration construct in VHDL generates parallel logic, not a sequence in time. If you try to write synthesizable VHDL, you should consider clocked logic and a real sequence.

 

[TrickyDicky]

As a start - this code wont even pass a syntax check as you have conflicting libraries. std_logic_arith and numeric_std both define types "unsigned" and "signed", and because you included both libraries, VHDL rules mean that both types are invisible, and hence the type conversions you have using unsigned wont compile.

To fix this, simply delete the non-standard synopsys std_logic_arith library. Never use it ever again.

Then you can work through the problems FvM points out. You appear to think VHDL is like writing software. Have you drawn a circuit diagram of your intended circuit? VHDL is a "hardware description language". Without understanding the hardware you expect to get, how do you expect to describe it?

I highly suggest you throw this code away and go and draw your expected circuit diagram.