CPLD of what Macro Cell size need to be used

Status
Not open for further replies.
E

embeddedlover

Full Member level 5
Joined
Aug 10, 2007
Messages
277
Helped
46
Reputation
92
Reaction score
38
Trophy points
1,308
Activity points
3,155
I have one application where i need to use CPLD as a bridge between I2C and UART.

Can anyone suggest how to proceed and what macro cell size of CPLD need to be used?
 

you mean how may logic you will consume. There is only one answer to that:
write the function, target a CPLD and implement.
I2C master - 160MC
I2 slave - 60MC
UART - typical a function implemented in an FPGA

Do you really need a CPLD? Flash based FPGA can keep the function non-volatile

BTW: Lattice's latest CPLD (called MachXO2) contains a hard coded I2C interface. It's just a matter of a couple of hours work to get the UART up and running
 
Last edited:
Do you really need a CPLD? Flash based FPGA can keep the function non-volatile
Click to expand...

As per my knowledge, CPLD is also non-volatile as it is based on EEPROM...
Even it has faster I/O response, that is why it can be used for control applications.



Can i also know how many MC required for implementing UART (simple TX, RX enough)?
Is it really necessary to go for FPGA? Can't we manage with CPLD?
Is there any thumb rule to determine how many macro cells a particular logic consumes?
 
You can expect 50 to 100 macro cells for the UART, depending on baud rate generator requirements etc.

The most simple way to know the exact resource usage is to write the behavioral code and synthesize it.

You also didn't tell a word about the intended bridge functionality. But the overall design size is obviously approaching 200 macro cells or somewhat more. I agree, that a flash based FPGA should be considered. Some devices marketed as CPLD are actually non-volatile FPGAs, e.g. Altera MAX II family.

Speed differences between FPGA and CPLD won't count for an UART or I2C design anyway.
 
I agree with FvM - speed doesn't count with the intended speed requirements.

CPLDs are however more considered for small control applications, with a fixed desired pin-to-pin delay (in the order of magnitude of 2.5 ...10ns). If that's the plan - or if your company rules dictate a CPLD architecture, then go for this solution. Otherwise pls consider a small FPGA - you will be by far less expensive. (big E²PROM CPLDs tend to cost a lot)
 
You also didn't tell a word about the intended bridge functionality
Click to expand...

I have a UART on one side and I2C on the other...wanted to use the device as protocol converter.

I was of the thinking upto know that CPLD costs much less than FPGA...
I also didn't get the use of volatile CPLDs....
 
I was of the thinking upto know that CPLD costs much less than FPGA...
Click to expand...
Not much less with 256 or more macro cells.
I also didn't get the use of volatile CPLDs....
Click to expand...
Nothing has said about volatile CPLD. In fact, they don't exist.
 
Low volume cost for a CPLD is around $1.50..$2.00 per 32MC. This means that for the 256MC (that's the minimum that you will need) $12..$16. If you look at online shops, you will find much higher prices.

I assume you can buy quite a lot of FPGA for this money..

In my opinion, you only have flash based (like MaxII, MaxV, MachXO, MachXO2 and others ) and E² based CPLDs (EPM7000, EPM3000, LC4K, Coolrunner2)
 
Information was very much helpful....

@FvM, LUCBRA
Can we discuss more on CPLDs and FPGA?
We shall go into basics and discuss if you are interested.
I am totally new to this...
 

embeddedlover said:
Information was very much helpful....

@FvM, LUCBRA
Can we discuss more on CPLDs and FPGA?
We shall go into basics and discuss if you are interested.
I am totally new to this...
Click to expand...

OK - but maybe you can start a new thread.
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…