CP-PLL floor plan considerations

i need to know the considerations must be taken in floor planning for CP/PLL for RF applications,

eg: which blocks should be away and which should be close ..

thanks in advance,..

as the basics of mixed signal IC design , the VCO and it's varactor are the most important blocks in the PLL , speical most of the phase noise come form the VCO

the varactor must be sheilded very well , the substarte arround it is tied good
also tie arround the inductor
the VCO must be away from the switching " noisy " digital circuits "
like pfd

design a good buffer for the VCO .

i wish this help

khouly

If you want to get good spur performance, I suggest the power for CP and VCO is different source to reduce the VCO coupling to charge pump.

Yibin.

thanks ,but i am asking about how to locate different PLL block in order to get the least interfernce and noise coupling,..

thanks in advance,.

that one is tricky.
a) split as much as you can the dividers and "analog" (CP, VCO) power supply.
b) guradrings /trenches usually help
c) distance - allow at least 50um of substrate (no substrate tie etc) between digital and analog portions. (hi resistive substrate help more than anything else)
d) you can shield VCO output, Vctrl etc with ground (kinda coax)

but the best is distance.... between structures, metal lines.....

Teddy said:

that one is tricky.
a) split as much as you can the dividers and "analog" (CP, VCO) power supply.
b) guradrings /trenches usually help
c) distance - allow at least 50um of substrate (no substrate tie etc) between digital and analog portions. (hi resistive substrate help more than anything else)
d) you can shield VCO output, Vctrl etc with ground (kinda coax)

but the best is distance.... between structures, metal lines.....

Click to expand...

thanks alot ,
but i think the CP is a noisy block as it cause supply glitches and its contols are at refrence freq. so haw can i make it share the VCO which is the most sensetive block for noise ??

regards

can somebody go into details of layout of a differential vco and some good methodologies for minimising phase noise with the layout.

regards
amarnath

but i think the CP is a noisy block as it cause supply glitches and its contols are at refrence freq. so haw can i make it share the VCO which is the most sensetive block for noise ??

Click to expand...

it's a bad idea to "share" CP with VCO.
put two noise blocks together will endup with more noise which u can not controll. I think Teddy's method is very good.

(kinda coax) : what does it mean ??

i think the meaning of kinda coax , is to sround the line with two grounds to reduces the coupled noise to it

abou the supply , i think u give a VCO a separated supply for CP , also u can make the CP near the phase detector , but not very much

but the most important thing that the noisey block must be apart from VCO

khouly

khouly said:

i think the meaning of kinda coax , is to sround the line with two grounds to reduces the coupled noise to it

Click to expand...

thanks for your reply i understand that it mean sheilding the line (Victim) from the aggressors (noisy line)

but i am asking what do kinda coax stands for

regards,..

ok - if you surround the signal line with gnd all arround you can calculate you will get simillar effect as a coaxial cable - not exactly but close. There is a whole theory what is the best spacing and stuff but it does not matter.

For the CP and VCO spacing - yes charge pump is a major source of jitter at Fcomp. Spacing of cca 50um on chip and decent substrate tie and perhaps well isolation (or trench) will help a lot.

Another thing one should consider is that output stage will probably modulate the power lines and the field arroud those could affect your VCO noise - do not put it too close.

Honestly it is all black magic - hard to prove (especially if you do not create testchips for it) so you should do what makes you feel good . For example I believe 45deg angles are must - electrons don't bump their heads to the wall....