[SOLVED] counting pulses in one second with vhdl

sam93 · Aug 12, 2015

hi dear friend. I used your advises and wrote the following code. in simulation ,when I use "std_logic_vector (25 downto0 )" instead of "integer range " for "c" and "counter_2" , the result for "c" is "xxxxxxxxxxxxxxxxxxxxxx"! what's should I do? thank you in advanced.
simulation is in ise.
vhdl code:

Code VHDL - [expand]
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entity tes is
port ( 
                    CLK_20M : in  STD_LOGIC;
                    CLK : in  STD_LOGIC;
                    b : out integer range 0 to 19999999;
                    c : out  integer range 0 to 19999999
               
                    );
end tes;
 
architecture Behavioral of tes is
 
signal cnt_1 : integer range 0 to 19999999 ;
 
begin
 
one:process(CLK)
    variable counter: integer range 0 to 19999999 ;
        begin
            if rising_edge(CLK) then
                counter := counter + 1;
            end if;
            cnt_1 <= counter;
            b <= cnt_1;
        end process;
 
two:process(CLK_20M)
    variable counter_2:  integer range 0 to 19999999 ;
        begin
            if (cnt_1 < 20000000) then
                if rising_edge(CLK_20M) then
                counter_2 := counter_2 + 1;
                end if;
            end if;
            c <= counter_2;
        end process;
 
end Behavioral;

TrickyDicky · Aug 12, 2015

you should debug it yourself by putting the signals that drive C on the wave window.

ads-ee · Aug 12, 2015

Code:

two:process(CLK_20M)
    variable counter_2:  integer range 0 to 19999999 ;
        begin
            if (cnt_1 < 20000000) then
                if rising_edge(CLK_20M) then
                counter_2 := counter_2 + 1;
                end if;
            end if;
            c <= counter_2;
        end process;
 
end Behavioral;

This doesn't match any flip-flop template I've seen. Does this even synthesize correctly?

And c getting assigned outside the if structure means it's combinational but it's not even in the sensitivity list. I'm thinking this is a simulation synthesis mismatch type of code.

You really need to look at examples of VHDL code for basic constructs and learn them, so you don't write VHDL software code.

wtr · Aug 19, 2015

Okay Sam.

1.
You get X's when a signal is not assigned. This can be because you have multiple assignments to the signal OR command is never run.

2.
In VHDL you have synthesisable code and non synthesisable code. What K-J posted earlier was none synth...since it used the keyword "after". Whereas people using a counter for timing are giving you synth code

3.
When generating a process you have essentially two types. Either combinatorial(full sensitivity list) or synchronous.

4.
Processes are run concurrently.

What you essentially want I guess is

Code:

#psuedo
Whilst within active second
  if pulse triggered
    count increment

Therefore

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combinatorial_Pulse : process (reset, pulse, active_sec)
begin
  if reset = '1' then
    count <= 0;
  elsif active_sec = '1' then
    if rising_edge(pulse) then
       count <= count + 1;
    end if;
  end if;
end process;
 
sync_active_sec : process(reset, clock)
begin
  -- manipulate clock such that you generate a 1 second train
  -- stuff
     active_sec <= '1';
  ---
end process;

Please mark topic as solved if this helps

sam93 · Aug 24, 2015

hi dears. the following code has result in isim, but on fpga board doesn't work. would you help me?
vhdl code

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
use ieee.numeric_std.all;
 
 
entity rez is
port ( 
                    CLK_20M : in  STD_LOGIC;
                    
                    );
end rez;
 
architecture Behavioral of rez is
 
signal a: std_logic_vector(25 downto 0);
signal clk_312khz :STD_LOGIC;-- 3.2 us
signal cnt_1: integer range 0 to 19999999 :=0 ;
signal cnt_2: integer range 0 to 67108863 :=0 ;
signal cnt_3: integer range 0 to 67108863 :=0 ;
signal enable : STD_LOGIC;
 
begin
 
clk_divider2:process (CLK_20M)  
    variable counter: std_logic_vector(8 downto 0) ; -- divider: 2^9
        begin       
                if rising_edge(CLK_20M) then
                    counter:=counter + 1;
                end if;
                clk_312khz <= counter(5);
                
        end process;    --clk_divider1
one:process(CLK_20M)
        begin
         
            if rising_edge(CLK_20M) then
                cnt_1 <= cnt_1 + 1 ;
                if (cnt_1 < 20000000) then
                   enable <= '1';
                   if (cnt_1 = 19999999) then
                      enable <= '0';
                   end if;
               end if;
           end if;
          
         end process;
two:process(clk_312khz)
        begin
            if (enable = '1') then
                if rising_edge(clk_312khz) then
                    cnt_2 <= cnt_2 + 1;
                 end if;
            end if;
            
        end process;
 
three:process(enable)
   begin
       if (enable = '0') then
                          cnt_3 <= cnt_2;
                          a <= std_logic_vector(to_signed(cnt_2,a'length));
                end if;
      end if;
    end process;
     
     
end Behavioral;

TrickyDicky · Aug 25, 2015

The problem is probably because you used logic generated clocks and asynchronous clock enables. You should not generate clocks with logic, you should use synchronous clock enable instead.

ads-ee · Aug 25, 2015

It's more likely that it doesn't work because there's no logic implemented. The design has no output, therefore everything would be removed as unused.

sam93 · Aug 25, 2015

hi. I did't the entire code, I just said about a part that's my problem.
entire code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
use ieee.numeric_std.all;
use work.asci_types.all;
 
entity rez is
port ( 
                    CLK_20M : in  STD_LOGIC;
                    SS2_A,SS2_B,SS2_C,SS2_D,SS2_E,SS2_F,SS2_G : out std_logic;
               SS1_A,SS1_B,SS1_C,SS1_D,SS1_E,SS1_F,SS1_G : out std_logic;
                    
                    LED : out STD_LOGIC_VECTOR (1 downto 0);
                    SW_1 : in std_logic;
                    
                    SW_DIP : in std_logic_vector(4 downto 1)
                    );
end rez;
 
architecture Behavioral of rez is
 
signal a: std_logic_vector(25 downto 0);
signal b: std_logic_vector(18 downto 0):="0011000011010100000"; --100,000
signal q: std_logic_vector(7 downto 0);
 
      
signal clk_312khz :STD_LOGIC;--led(1),,, 3.2 us
 
signal clk_624khz :STD_LOGIC;
 
signal DISP1:std_logic_vector(6 downto 0);
signal DISP2:std_logic_vector(6 downto 0);
 
signal cnt_1: integer range 0 to 19999999 :=0 ;
signal cnt_2: integer range 0 to 67108863 :=0 ;
signal cnt_3: integer range 0 to 67108863 :=0 ;
 
signal enable : STD_LOGIC;-- led(0)
 
begin
 
 
 
        
clk_divider2:process (CLK_20M)  
    variable counter: std_logic_vector(8 downto 0) ; -- divider: 2^9
        begin       --begin  process of clk_divider_for_threstor driver
                if rising_edge(CLK_20M) then
                    counter:=counter + 1;
                end if;
                clk_312khz <= counter(5);
                clk_624khz <= counter(4);
        end process;    --clk_divider1
 
 
one:process(CLK_20M)
        begin
         if (SW_DIP > "0000") then 
            if rising_edge(CLK_20M) then
                cnt_1 <= cnt_1 + 1 ;
                if (cnt_1 < 20000000) then
                   enable <= '1';
                   if (cnt_1 = 19999999) then
                      enable <= '0';
                   end if;
               end if;
           end if;
           end if;
         end process;
 
two:process(clk_312khz)
        begin
            if (enable = '1') then
                if rising_edge(clk_312khz) then
                    cnt_2 <= cnt_2 + 1;
                 end if;
                 else
                 cnt_2 <=0;
            end if;
            
        end process;
 
three:process(enable)
   begin
       if (enable = '0') then
          
                          cnt_3 <= cnt_2;
                          a <= std_logic_vector(to_signed(cnt_2,a'length));
                
      end if;
    end process;
     
     div_3: Process (clk_312khz,a,b)
    variable d: std_logic_vector(25 downto 0);
        Begin
            if (a(25 downto 7) >= b) then --7
                q(7) <= '1';
                d:= (( '0' &'0' &'0' &'0' &'0' &'0' &'0' & a(25 downto 7))- ( '0' &'0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(6);
            else
                q(7)  <= '0';
                d:= ( '0' &'0' &'0' &'0' &'0' &'0' & a(25 downto 6));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --6
                q(6) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(5); 
            else 
                q(6) <='0';
                d:= ( d(24 downto 0) & a(5));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then  --5
                q(5) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(4); 
            else 
                q(5) <='0';
                d:= ( d(24 downto 0) & a(4));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --4
                q(4) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(3); 
            else 
                q(4) <='0';
                d:= ( d(24 downto 0) & a(3));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --3
                q(3) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(2); 
            else 
                q(3) <='0';
                d:= ( d(24 downto 0) & a(2));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --2
                q(2) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(1); 
            else 
                q(2) <='0';
                d:= ( d(24 downto 0) & a(1));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --1
                q(1) <= '1';
                d:= (d- ('0' & '0' &'0' &'0' &'0' &'0' &'0' & b));  
                d:= d(24 downto 0) & a(0); 
            else 
                q(1) <='0';
                d:= ( d(24 downto 0) & a(0));
            end if;
            
            if (d>=('0' & '0' &'0' &'0' &'0' &'0' &'0' & b)) then --0
                q(0) <= '1';
            else 
                q(0) <='0';
            end if;
    
      case q(3 downto 0) is
   when "0000" => DISP1 <= "1111110"; --0
    when "0001"=> DISP1 <="0110000";--1
    when "0010"=> DISP1 <="1101101";--2
    when "0011"=> DISP1 <= "1111001";--3
    when "0100"=> DISP1 <="0110011" ;--4
    when "0101"=> DISP1 <="1011011";--5
    when "0110"=> DISP1 <=  "1011111";--6
    when "0111"=> DISP1 <="1110000";--7
    when "1000"=> DISP1 <="1111111";--8
    when "1001"=> DISP1 <="1111011";--9
    when "1010"=> DISP1 <="1110111";--A
    when "1011"=> DISP1 <="0011111";--b
    when "1100"=> DISP1 <="1001110";--C
   when "1101"=> DISP1 <="0111101";--d  
   when "1110"=> DISP1 <="1001111";--E
   when "1111"=> DISP1 <="1000111";--F  
    when others => DISP1 <="1111111";     -- display off
    end case; 
 
SS1_A <=  DISP1(6);
SS1_B <=   DISP1(5);
SS1_C <=   DISP1(4);
SS1_D <=   DISP1(3);
SS1_E <=   DISP1(2);
SS1_F <=   DISP1(1);
SS1_G <=   DISP1(0);
 
   case q(7 downto 4) is
   when "0000" => DISP2 <= "1111110"; --0
    when "0001"=>  DISP2 <="0110000";--1
    when "0010"=> DISP2 <="1101101";--2
    when "0011"=> DISP2 <= "1111001";--3
    when "0100"=> DISP2 <="0110011" ;--4
    when "0101"=> DISP2 <="1011011";--5
    when "0110"=> DISP2 <=  "1011111";--6
    when "0111"=> DISP2 <="1110000";--7
    when "1000"=> DISP2 <="1111111";--8
    when "1001"=> DISP2 <="1111011";--9
    when "1010"=> DISP2 <="1110111";--A
    when "1011"=> DISP2 <="0011111";--b
    when "1100"=> DISP2 <="1001110";--C
   when "1101"=> DISP2 <="0111101";--d  
   when "1110"=> DISP2 <="1001111";--E
   when "1111"=> DISP2 <="1000111";--F  
    when others => DISP2 <="1111111";     -- display off    end case; 
end case; 
SS2_A <=  DISP2(6);
SS2_B <=  DISP2(5);
SS2_C <=  DISP2(4);
SS2_D <=  DISP2(3);
SS2_E <=  DISP2(2);
SS2_F <=  DISP2(1);
SS2_G <=  DISP2(0);
 
end process;
LED(0) <= enable;
LED(1) <= clk_312khz;
end Behavioral;

ads-ee · Aug 25, 2015

There are so many things wrong with this code. You absolutely have to read a VHDL book and a digital design book. Your HDL doesn't even represent valid synthesizable logic. The synthesis tool is probably trying to implement what you've written but I imagine it's not doing exactly what you would expect.

if statements surrounding the clock events? I'm not sure if it will implement an enable control or not, might end up with a gated clock. I honestly don't know, as I've never tried writing code like this.

You're generating clocks in logic instead of clock enables (very bad in an FPGA).

You've got variables being used. Not a good idea for anyone but advanced VHDL users as there can be subtle gotchas. Especially in this case because you are writing the code like a software programmer. d is also read in the process, but as it's a variable it doesn't cause the process to be entered when it changes. Once again I never write code like this so I'm not sure what the logic synthesizes to. But you've also got a clock in the sensitivity list which will like make the results of the simulation different than the real world as there is nothing in the process that is clocked.

Code:

 d:= (( '0' &'0' &'0' &'0' &'0' &'0' &'0' & a(25 downto 7))- ( '0' &'0' &'0' &'0' &'0' &'0' &'0' & b));  
 d:= d(24 downto 0) & a(6);

This reassigns d a second time in the same clock cycle. In my opinion this is bad coding style. Oh, but wait the process isn't clocked but is combinational, have no idea what the synthesis tool does with this. I think I'd have to be a VHDL super duper expert to even understand what you're code would synthesize to.

You're got numeric_std called out but then proceed to ignore the fact and keep using the std_logic_unsigned (the non-IEEE standard synopsys package, which is not necessarily supported in a uniform manner between vendors). Use the IEEE package and do the math with the correct types.

You should go and look at example code on something like http://esd.cs.ucr.edu/labs/tutorial/. The code on that site gives reasonable examples of various structures you would typically use and how to code them for synthesis. And when you look at the code there you'll see they don't make clock enables on flip-flops like you do.

wtr · Aug 28, 2015

To reiterate what Ads-ee was talking about

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two:process(clk_312khz)
        begin
          if rising_edge(clk_312khz) then -- this should be added
            if (enable = '1') then
--                if rising_edge(clk_312khz) then -- this should be removed.
                    cnt_2 <= cnt_2 + 1;
--                 end if;
                 else
                 cnt_2 <=0;
            end if;
            
end process;

In VHDL the sensitivity list is used to trigger the process.. Therefore your conditions must somehow relate to the triggers.

You repeat this type of mistake in process one too.

Given that you only have enable as zero for one clock cycle you should have process three being synchronous such that

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three:process(clk_20M)
   begin
     if rising_edge(clk_20M) then
       if (enable = '0') then
         cnt_3 <= cnt_2;
         a <= std_logic_vector(to_signed(cnt_2,a'length));
      end if;
    end if;
end process;

[SOLVED] counting pulses in one second with vhdl

sam93

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TrickyDicky

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wtr

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sam93

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TrickyDicky

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sam93

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Code VHDL - [expand]
1 2 3 4 5 6 7 8 9	three:process(clk_20M) begin if rising_edge(clk_20M) then if (enable = '0') then cnt_3 <= cnt_2; a <= std_logic_vector(to_signed(cnt_2,a'length)); end if; end if; end process;

[SOLVED] counting pulses in one second with vhdl

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