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[SOLVED] counting pulses in one second with vhdl

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sam93

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hi, I need to counting pulses of a input in 1 second in my project. I don't know how to create 1 second signal. would you help me?
thank you.
 

If you don't know how to create a 1 second signal, you've got big problems. But here's how to to do it: divide your clock by the number equal to the frequency. In other words, if you've got a 1MHz clock, divide it by 1 million.
 

And Barry isn't saying you divide a 1 MHz clock using: 1MHz/1000000.

Use a counter running off of the 1 MHz clock that counts from 0 to 999,999 (note one less than 1 million). Each time it rolls over from 999,999-->0 is 1 second.
 

sam93 said:
hi, I need to counting pulses of a input in 1 second in my project. I don't know how to create 1 second signal. would you help me?
Click to expand...

x <= '1', '0' after 1 sec;

Kevin
 

Kevin, that's evil. 8-O I'm sure they'll be back here asking why their design doesn't work on their board.
 

hi, actually my problem is that I can't create 1 second "high" signal!
Dear ads-ee, K-J and barry! I shouldn't use a clock and a couter to create it!
 

well the use an oscillator feed in signal.....xtal, RC, etc.! :)
 

sam93 said:
hi, actually my problem is that I can't create 1 second "high" signal!
Dear ads-ee, K-J and barry! I shouldn't use a clock and a couter to create it!
Click to expand...

So you mean you only want simulation code? If so then see K-J's post for VHDL.

Here is a generating a 1 second high pulse after waiting .1 seconds from the start of simulation
Code Verilog - [expand]
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`timescale 1ps/1ps
localparam s = 1000000000;
reg high_signal;
initial begin
  high_signal <= 1'b0;
  #(0.1*s);  // delay for 0.1 second
  high_signal <= 1'b1;
  #(1*s);  // 1 second pulse on high_signal
  high_signal <= 1'b0;
end


If this isn't what you have in mind then give us a better specification of what the requirements are.
 

sam93 said:
hi, actually my problem is that I can't create 1 second "high" signal!
Dear ads-ee, K-J and barry! I shouldn't use a clock and a couter to create it!
Click to expand...

Well, if you don't have a clock, it's going to be pretty difficult. Maybe you could hook your pulses up to an amplifier that blinks an LED and then drop a Faberge egg from a height of 4.9 meters and start counting blinks of the LED. When the Faberge egg breaks, stop counting.
 

sam93 said:
hi, actually my problem is that I can't create 1 second "high" signal!
Dear ads-ee, K-J and barry! I shouldn't use a clock and a couter to create it!
Click to expand...
The solution I posted in #4 meets all of your stated requirements.

Kevin
 

HI. would you explain it in vhdl?
 

x <= '1', '0' after 1 sec;

Kevin
Click to expand...
Kevin's karma just dropped 100 points.

Assuming a 1MHz input clock, this will create a "one shot" ramp from '1' to '0'. It will happen one second after system reset.
Code: 
constant one_million : natural := 1000000 ;
signal counter : natural ;
signal pulse : std_logic ;

process ( clock ) is 
begin
  if reset = '1' then
    pulse  <= '1' ;
    counter <= ( others => '0' ) ;
  elsif rising_edge ( clock ) then
    if counter = one_milion - 1 then
      pulse  <= '0' ; 
    else
      counter <= counter + 1 ;
    end if ;
  end if ;
end process ;
 

shaiko said:
Kevin's karma just dropped 100 points.
Assuming a 1MHz input clock, this will create a "one shot" ramp from '1' to '0'.
Click to expand...
According to post #6, the OP says this must be done without a clock so your solution does not meet requirements.
Karma is still good. Mine is still the only solution that meets all of the stated requirements.

Kevin
 

According to post #6, the OP says this must be done without a clock so your solution does not meet requirements.
Karma is still good. Mine is still the only solution that meets all of the stated requirements.
Click to expand...

Yes, exactly. I would consider the possible case that the poster is simply confused about the problem. Unfortunately we can only guess about his intentions. The solution "without a clock" doesn't make much sense, except being a strange homework problem.
 

Hi, dear friends. Maybe I didn’t explain enough at #6.
My problem: I have to counting a clock (that is unknown period and frequency) in just 1 second.
When I use another clock (like 20 MHz) to create 1 second, I faced to this error in ISE :
“Xst:1534 - Sequential logic for node <a> appears to be controlled by multiple clocks.”
My vhdl code:
Code VHDL - [expand]
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[B]signal b: std_logic_vector(18 downto 0);
Process (CLK_20M)
variable counter: integer range 0 to 67108863 ; --26 bits 67108863
        Begin
            if rising_edge(CLK_20M) then
        counter:=counter + 1;
            if (counter < 20000000) then
                if rising_edge(clock) then 
                          a <= a + 1;
                end if;
            end if;
    end if;
end process;[/B]
 
Last edited:

So it turns out that your statement in post #6 "I shouldn't use a clock" is completely misleading.

You actually have a clock (and must use a clock) to generate the 1 second gate time for your frequency counter.

It's a design involving two clock domains and domain crossing signals, it surely doesn't work by nesting clock sensitive events in a process.

Plan to have two processes, one for each clock. Generate the gate signal in one process, synchronize it to the other process by state-of-the-art synchronisation methods (a FF chain should work in this case) and make it control the frequency counter.
 
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    sam93

    Points: 2
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This sounds like you are supposed to take 20 million samples of this "clock" and found out it's perioud based on number of high and low cycles in the period.
You cannot have a process controled by two clocks - think about it - you're trying to detect an edge exactly co-incident with another edge. Impossible
 

sam93 said:
Hi, dear friends. Maybe I didn’t explain enough at #6.
My problem: I have to counting a clock (that is unknown period and frequency) in just 1 second.
When I use another clock (like 20 MHz) to create 1 second, I faced to this error in ISE :
“Xst:1534 - Sequential logic for node <a> appears to be controlled by multiple clocks.”
My vhdl code:
Code VHDL - [expand]
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[B]signal b: std_logic_vector(18 downto 0);
Process (CLK_20M)
variable counter: integer range 0 to 67108863 ; --26 bits 67108863
        Begin
            if rising_edge(CLK_20M) then
        counter:=counter + 1;
            if (counter < 20000000) then
                if rising_edge(clock) then 
                          a <= a + 1;
                end if;
            end if;
    end if;
end process;[/B]
Click to expand...

Now you are giving us this code, which is almost the same as the previous thread on binary division. Where you were told in no uncertain terms that the code was not synthesizable and did not make any sense.

Previous thread code of a 1 second counter that is used to "count" how many encoder_hallsensor_b's occur.
Code VHDL - [expand]
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process (CLK_20M) 
   constant a : std_logic := "1000111101110000000"; --293760 
    variable counter: std_logic_vector(25 downto 0) ;  ;--26 bits 67108863
    variable count:std_logic_vector(25 downto 0) ;  ;--26 bits
    variable rps: std_logic_vector(7 downto 0) ; -- 8 bits 255
        begin       
                if rising_edge(CLK_20M) then
                    counter:=counter + 1;
                    if (counter > 20000000) then
                        counter := (others => '0');
                    elsif rising_edge(ENCODER_HALLSENSOR_B) then 
                        count := count + 1;
                    end if;
                end if;
                rpss := count/a;


You really want to do something like this:
Code VHDL - [expand]
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-- count seconds
process (clk20m)
begin
  if rising_edge (clk20m) then
    sec_count <= sec_count + 1;
    if (sec_count = 20000000-1) then
      sec_count <= 0;
      one_sec <= not one_sec;
    end if;
  end if;
end process;
 
-- count encoder edge
process (enc_clk)
begin
  -- synchronizer
  one_sec_1 <= one_sec;
  one_sec_2 <= one_sec_1;
  -- edge detect
  one_sec_3 <= one_sec_2;
  one_second <= one_sec_3 xor one_sec_2;
 
  -- encoder counter
  if (one_sec_3) then
    encoder_count <= count;
    count <= 0;
  else
    count <= count + 1;
  end if;
end process;

See if that does what you want, or if it even compiles (I didn't check)
 

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