counter out of SIPO shift register

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neazoi

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Can a counter be made out of a SIPO shift register? I think Yes.
What are the advantages instead of the decade counter?
 

I am thinking it in a memory address decoder. you load the adress serially and once it is loaded, you read the data outputs.
Less cabling
 

Both the counter and the shift register falls in the family of sequential logic and they perform different tasks.

The SIPO upon bringing out the parallel output latches the outputs unless it is configured to be a ring or cyclic design but the counter will continue to count.

I think the main advantage is in memory design (as we know parallel output tends to be faster).
 
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