dareon
Newbie level 5
Spartan 3 with Xilinx ISE11.5
I need to make some routine that will delay some routines on my FPGA for a set amount of time. The code I have chosen to do this is below and is a simple counter with initial values.
I also have a variable that will change to 1 once the counter has counted to a certain value( I want to continue to use the counter after). However, when I do this I get the warning.
WARNING:Xst:1426 - The value init of the FF/Latch STARTUP hinder the constant cleaning in the block Top.
You should achieve better results by setting this init to 1.
The code is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Top is
Port (
CLK : in std_logic; -- Master Clock F=60 MHz
OUTER : out std_logic;
DPDATA : inout STD_LOGIC_VECTOR(7 downto 0));
end Top;
architecture Behavioral of Top is
signal STARTUPCNT : unsigned(15 downto 0) := "0000000000000000";
signal STARTUP : STD_LOGIC := '0';
begin
STARTUPCOUNT: process(CLK)
begin
if rising_edge(CLK) then
STARTUPCNT <= STARTUPCNT + 1;
if STARTUPCNT = "0111111111111111" then
STARTUP <= '1';
DPDATA <= "11111111";
else
STARTUP <= STARTUP;
DPDATA <= "00000000";
end if;
end if;
end process;
Outer <= STARTUP;
end Behavioral;
The description xilinx gives for the error is
This warning occurs when a register with an INIT value (the initialization value that a memory element has when the FPGA is powered on) has a constant input that does not match the INIT value and no other control signal (such as a local set/reset). The constant input might be due to an undriven input or logic optimization.
To avoid the warning, examine the logic value and/or trimming at the input signal of the register. If the values of the input and INIT match, XST will be able to optimize the registers using constant optimization.
It is almost as if my counter value is not initializing correctly.
Most likely I am just doing something stupid :-/
Thank You
Russell
I need to make some routine that will delay some routines on my FPGA for a set amount of time. The code I have chosen to do this is below and is a simple counter with initial values.
I also have a variable that will change to 1 once the counter has counted to a certain value( I want to continue to use the counter after). However, when I do this I get the warning.
WARNING:Xst:1426 - The value init of the FF/Latch STARTUP hinder the constant cleaning in the block Top.
You should achieve better results by setting this init to 1.
The code is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Top is
Port (
CLK : in std_logic; -- Master Clock F=60 MHz
OUTER : out std_logic;
DPDATA : inout STD_LOGIC_VECTOR(7 downto 0));
end Top;
architecture Behavioral of Top is
signal STARTUPCNT : unsigned(15 downto 0) := "0000000000000000";
signal STARTUP : STD_LOGIC := '0';
begin
STARTUPCOUNT: process(CLK)
begin
if rising_edge(CLK) then
STARTUPCNT <= STARTUPCNT + 1;
if STARTUPCNT = "0111111111111111" then
STARTUP <= '1';
DPDATA <= "11111111";
else
STARTUP <= STARTUP;
DPDATA <= "00000000";
end if;
end if;
end process;
Outer <= STARTUP;
end Behavioral;
The description xilinx gives for the error is
This warning occurs when a register with an INIT value (the initialization value that a memory element has when the FPGA is powered on) has a constant input that does not match the INIT value and no other control signal (such as a local set/reset). The constant input might be due to an undriven input or logic optimization.
To avoid the warning, examine the logic value and/or trimming at the input signal of the register. If the values of the input and INIT match, XST will be able to optimize the registers using constant optimization.
It is almost as if my counter value is not initializing correctly.
Most likely I am just doing something stupid :-/
Thank You
Russell