could vhdl + verilog codes are syntsisable ???????

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tom_hanks

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i have a piece of VHDL code which I synsithsis and everything worked properly..
now I am writing verilog code for asynchrous Tr-Rx..
I want to include my VHDL code with verilog?
does it possible..??

can i add boths, netlist and download it on FPGA..

is there any EDA tool for this?

TIA,
tom
 

In Alteras Quartus (I think also in Xilinx ISE and others) you can mix both VHDL/Verilog code and even others (like schematics). But for example if topfile is Verilog than you should add a wrapper verilog code for your VHDL module to include it.

This topic has already been discussed here at:
 

Hi!
in ISEWebpack 5.2 n up u can do it. but if u go for schematic design i think it is going to be very easy task as there u dont have to write the code to connect both the modules instead u just have to call up the components an link them with nets n wires directly n ur synthesisable code would be generated automatically.

bye
Ashish
 

mentor's Fpga adv@ntage can also do this

Best regard
 

Hi.

FPGA tools able to perform mixed HDL synthesis, and in order to perform simulation, you need a simulator that having this Mixed HDL feature.. Modelsim having this feature, but you need to purchase a license from Modeltech. Altera quartus able to perform the simulation with mixed hdl, but i believe it is very very slow...
 

hiya,
can u give some idea about the mentor's Fpga adv@ntage...
do u have demo or tutorial of this pack?

tom
 

any tools can do mixed-hdl design. just beware the interface(instanciation) of verilog and vhdl modules.
 

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