could calibre lvs do not check mosfet B term

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jie.houmo

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Hi,I have some question about calibre lvs rule ,is there any command or option could filter the B term connection.I want when i correctly connect a mosfet G S D and lvs could pass
 

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jjx said:
Could you clarify the question?
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jjx said:
Could you clarify the questicalibre
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thanks for reply.
such as a mos ,when run lvs ,calibre will compare connection of G S D B ,all the four terms of mos,I want ask if there is some method that could make calibre only compare G S D without body connection,whatever body connect floating or connected to other wrong net.
 

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Far better for you to create schematics which properly express the
B terminal connecticity, and get a passing result that way. If you
force B connections to be ignored, there is a chance that you
will allow / miss wrong ones.

Basic CMOS will make the NMOS devices share a common sub!
connection, SOI or multi-well may produce "floating" bodies
and this may in turn cause some circuit misbehaviors at test or
in application (whether or not they are exposed by any design
simulations - I've had to struggle to get floating-body-
consequences-accuracy on SOI flows).
 

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thanks for reply.I want to ignore body connection because our major circuit is sram array,there is only on power and and of course one ground net,it is hard to have a wrong connect to body.And usually a bottem cell's well would not connect to specially power or ground in layout.so when I run lvs,I have to add well connection in the bottom cell but if it is used in top cell,I have to remove the tap.So I try to find some method that lvs could ignore the B terminal to reduce some unnessacessaty work in layout.
 

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As freebird, I would also strongly suggest not to fool the tool too much. I see what you mean with the approach and that you are pretty certain, etc., and if it was a single-click button in calibre, it would be nice.

It's hard for calibre to know exactly which node you mean, it should be possible to stamp the bulk to ground in the rules file.

For these kind of cases, I use a mask layout in which I instantiate the cell I want to test. You can still LVS against the same schematic.
 

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