Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Copper Spacing in PCB designing

Status
Not open for further replies.

gowthaman90.d

Newbie level 3
Newbie level 3
Joined
Mar 14, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,323
Hi all,

I have some doubts regarding the Design For Manufacturing(DFM)

I wonder why we need to maintain more spacing for shapes in PCB.

For Ex trace(copper) to other elements we will maintain 0.2 mm gap and Shapes(Copper) to other elements we will maintain 0.4 mm. Can anybody explain the reason for this?
 

I use one spacing distance for all copper to copper on a std. board.
 

Yeah I've never heard of using different spacing. Is this spec coming from the fab house, in that case I would respect it. If its just something you saw online I'd say screw it. I've never had problems spacing shapes even less that 0.2mm through Sierra or Advanced Circuits.
 

Yeah I've never heard of using different spacing. Is this spec coming from the fab house, in that case I would respect it. If its just something you saw online I'd say screw it. I've never had problems spacing shapes even less that 0.2mm through Sierra or Advanced Circuits.

I didn't see this in online...I am working in PCB design and Substrate design for Ics using Cadence Allegro tools..There is seperate spacing constraints for pouring dynamic Shapes from our manufacturers. If anybody knows answer for this..pls explain...
 

There may be application specific reasons to set different defaults for individual spacing constraints, asking for a general answer doesn't make much sense however. If track to track spacing is marginal, you may want to mitigate those constraints that are not essential for design density. A trivial explanation could be that the DFM rules had been edited for a new design, but incompletely.

In my view, the question brings up a simple counter question. Do you understand the technology parameters behind the present design rules? If not, you should enquire about it.
 

Its is probably for controlling etch compensation or to allow wider manufacturing tolerances.during the fabrication process, most CAD packages allow for different spacing's between certain copper features such as Pads, tracks, copper etc.
The link below is a start, lots of info on PCB manufacturing process, having a basic understanding will help you design boards that can be made...


**broken link removed**
 

That situation you said do exist but not common,we often design the same spacing on a board, apart from we need achieve some special functions.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top