Hello Tony,
Thank you for the reply. The transmission line is designed for 50 ohm. Please find the attached screenshot. However, I am not getting the constant 50 ohm impedance for overall frequency.According to impedance curve, we see TL Z0 of about 29 ohm, terminated with 50 ohm.
Yes, I am using exact same width and spacing in HFSS like ADS. Screenshot attached; In HFSS for now to make it more simpler I am using rectangular sheet (0 thickness and perfect conductor). Do you think this is making difference? Yes, I understand 0.05mm spacing is not possible in PCB technologies. Actually, I am using other substrate for which 0.05mm is possible but to make myself clear in concepts, I am using FR4 substrate before diving into actual substrate. Also, I am limited to CPW not in Grounded CPW. Thank you again for your help.I wonder if you have used exactly the same geometry in HFSS and in Linecalc? Linecalc shows rather unphysical conductor height of 0.15 um. If you had e.g. used 0.15 mm in HFSS, the impedance value would be plausible. This can be only checked in HFSS model.
I would also comment that 0,05 mm ground separation can't be manufactured in most PCB technologies, and if you have an advanced technologie supporting this structure width, it won't be very accurate.
Post #2 suggests Saturn PCB toolkit, but it doesn't support CPW without ground or different counductor height for CPW.
Please find the attached screenshot for the zoomed version of port which is similar in other end with lumped RLC element. I did two port simulation as well and calculated input impedance using relation1) Please show a zoomed in view of your port configuration.
View attachment 185811
2) Your approach to use a lumped termination instead of port 2 is unusual. You should figure how how to get Zin (not Z11!) from 2-port simulation in HFSS. Many EM solvers have such Zin parameter readily available, otherwise you can calculate it from S11.
3) Have you included metal thickness in simulation? It will be relevant at this extremely narrow gap. Also, in real world the solder mask will have a strong effect at this narrow gap width, not to mention FR4 fibre pattern ...
It is difficult to understand what we see here. You have some length standing out at the end, extending over the PCB substrate material?Please find the attached screenshot for the zoomed version of port which is similar in other end with lumped RLC element.
Yeah that was connecting two grounding plane together and assigning lumped port in between. However, I changed the structure and put it inside. I have attached screenshot of whole design and port connection here. The port used is lumped port. The length and width of the port are equal to width of the signal trace which is in between the signal trace and two merged ground.It is difficult to understand what we see here. You have some length standing out at the end, extending over the PCB substrate material?
What port type did you use? I don't see any port in your screenshot. A short lumped port length would mean large parasitic C from signal to ground conductor across the port, and HFSS has no port calibration to remove that effect.
Thank you so much for the guidance and observing phase S21 to verify if designed transmission line is lambda/2 is a great idea. I designed the wave port accordingly. The S21 phase is around 178 degree and input impedance seems to be little off which I believe is related to thickness of PEC backing needed in wave port since changing the thickness is taking me closer to 50 ohms and 180 degrees. When I change the port impedance to 70 ohms the input impedance is 66ohms which is quite a bit off. I checked HFSS manual and there is no any explanation related to thickness of PEC backing. Could you please help me what should be the thickness of PEC backing or if it is related to something else? I am looking for exact ZL impedance in input impedance at least in simulating platform like circuit simulator since after this I am designing a matching network for different load using transformer and so on and input impedance having little off also change a lot. I highly appreciate your help on this.You are using many strange test methods.
Why don't you look at S-parameters to verify that S21 phase is 180°?
But anyway, I built my own 3D EM model using your dimensions, using Empire XPU (FDTD) solver. I used a wave port (QTEM port) and get very good matching, return loss is better than 30dB. Metal is zero thickness, as you modelled in linecalc. Screenshots below!
So the issue is your HFSS model. I would recommend that you look at post #11: using wave ports will avoid possible error sources from port parasitics. But there are many other possible mistakes in using EM solvers, so take your time to learn using the tool!
View attachment 185891
View attachment 185892
Simulated line impedance should not depend on port impedance!When I change the port impedance to 70 ohms the input impedance is 66ohms which is quite a bit off.
Simulated line impedance should not depend on port impedance!
Not sure why you get 66 Ohm. My line impedance result for your dimensions is around 45 Ohm, for pure CPW on the top layer with not metal on PCB Bottom layer.
I cannot help you with HFSS port setup, but others who are more familiar with HFSS might jump in. And of course, there are dozens of settings in HFSS which have an influence on accuracy. Why don't you post your HFSS model, so that other users can check what your mistake is?
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