Trying to bait me to this thread with a "Helpful post rating"? You clever little monkey you!
Couple of points you are free to ignore:
A review date is noone's problem but yours. Time management is such a wonderful thing. I know this because by nature I totally **** at it.
But for some reason or other it seems time management is a very useful skill to have as an engineer. Besides, it's a review. Just cook up some bullshit argument why it's not done yet to buy you some time, and then you have another week to do the proper work. Thera ya go!
I totally ignored the post because while you may think you have given all the details, you only sortof have. So I was hoping someone else was willing to go through the totally obvious future back and forth of "here, this is the solution for the problem you specified. --- Nono, I need also a blinkenlights. --- Okay, here is a solution for a blinkenlights. --- Oh yes, and I also need to update the blinkenlights over RS232. --- etc".
What am I on about?
First you only mentioned you needed a .ceo file
Then 10 days later you come up with:
using EDK software i wanna give an image to fpga through serial port RS232 providing a SDRAM
So who knows what you will come up next. ;-)
And IFF I understand your requirements correctly, these are two entirely seperate problems. For convenience I am assuming you don't actually mean a .ceo file but do in fact mean a .coe file. Right? Right.
Code:
; http://www.xilinx.com/itp/xilinx10/isehelp/cgn_r_coe_file_syntax.htm
; http://www.xilinx.com/support/answers/11744.htm
;
; Sample initialization file for a
; 8-bit wide by 32 deep RAM
memory_initialization_radix = 16;
memory_initialization_vector =
1002, 3004, 5006, 7008, A00B, CD, EF, 12, 34, 56, 78, 90, AA, A5, 5A, BA,
77, 43, 65, 87, BA, DC, FE, 21, 43, 65, 87, 09, 1A, 88, 99, 33,
00, 11, 22, 33, 44, 55, 66, 77, 88, 99, AA, BB, CC, DD, EE, FF;
There, an example .coe file which incidentally is literally the first one I found in some test project directory I had. As you can see it's totally easy to read and generate using whatever tool you fancy. I'm sure xilinx may even have some tools for it. The careful reader may or may not note that the comment in this particular header may or may not be pedagogically sound at this point in time.
The .coe file is the easiest. All the .coe is, is just a static file that gets used during synthesis. So during synthesis the xilinx tools read the .coe and use that to bram initial data in the bitstream. Then during configuration (when your .bit file is put in the fpga) the actual data is stored in the BRAM. That is easy enough that you should get it working before the 20th, assuming you have the rest already working. Oh wait, psychology, yeah right sorry, my bad! Disregard that false hope I just gave. Do not disregard the fact about this being the easiest part however.
The point there is to get the .coe business working first, and only then start worrying about your RS232 stuff.
What RS232 stuff? Oh the RS232 stuff you made up 10 days after you gave the initial problem. Do you read Dilbert?
So the RS232 stuff ... If I understand you correctly you want to first initialize it with a .coe file. That way whenever you powerup the device and it configures then it will show the initial picture based on the data in that .coe file.
And then AFTER the powerup you want to be able to send it updates with new picture data. Yes? Cool. That's an entirely different thing, which incidentally is also more work than just the static pic from the .coe file. What you need here is some way to update your BRAM content, and apparently by using RS232 link.
So you'll need an UART + a small FSM to do the BRAM updates for you.
If "yes" you do need the static pic AND the updates as I'm guessing from your posts, and "no, I don't know what the hell you are on about with that UART + FSM" then I suggest forget that until the 21st. Just get a static pic working so they can go "ooooooh aaaaaah static pic!" during the review. And then after that worry about getting an UART + FSM working.
Possibly you could also use chipscope to do quick and dirty bram updates IF you are already familiar with it. If not then the UART + FSM is faster. That, and it will pass a final review, which I doubt any chipscope solution will.
Oh yeah, one last quick tip. I assume you want to do updates AND still be able to show the pic at the same time. Which means you will still be doing BRAM reads (to show the picture) while at the same time you want to do BRAM writes (to update the picture). If so, you want to make this a dual port BRAM with a read and a write port.
---------- Post added at 17:41 ---------- Previous post was at 16:50 ----------
Since certain very specific locations sometimes have google outages here's one google hit by proxy:
Initializing BRAM via CoreGen File Size Problem - Xilinx User Community Forums