EDA_hg81
Advanced Member level 2
Code:
ini: process ( armclkout, inistatus )
begin
if ( rising_edge( armclkout ) ) then
soiclkcon <= soiclkcon + 1;
if ( soiclkcon = spiclk_gen ) then
soiclkcon <= x"00";
spiclk <= not spiclk;
elsif ( soiclkcon = x"1F" and spiclk = '0' ) then
case inistatus is
when x"00" =>
..
when x"01" =>
..
when others => null;
end case;
end if;
end if;
end process;
In this code I am using a clock divider to generate a new clock from 50MHZ to 400KHZ.
“elsif ( soiclkcon = x"1F" and spiclk = '0' ) then” this line is used to capture data in 400KHZ domain.
The FSM is use for data processing in 400KHZ domain.
Do you think this structure is good or not?
Thank you for your any suggestions.