Conversion of RTL to spice

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bastos4321

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verilog2spice

I'm an analog designer, but recently I need to convert an RTL file to spice netlist for simulation. I have the spice netlist of the used gates. How can I convert the RTL code to spice, and which tool to use.

Could some one help. Thanks

Bastos
 

uses design compiler synthesis your rtl code, you can write verilog netlist, then convert verilog netlist into spice netlist(not sure which tool can do it right), you need include the spice netlist of std cells with the converted spice netlist of your circuit.
 

basically what you need is to convert from EDIF to SPICE .. i think that can be done with E-STUDIO!

Just to confirm . Yes that can be done with E-studio ..But you need all the MODELS for the tecnology you used to write your RTL flow ..Otherwise they will show up as subcircuits.
 

Thanks I will try that. I have the subcircuit description of each gate and the hspice models. I just want to check the functionality not timmings.

Regards bastos
 

You can try verilog2spice of nassda, it's include in hsim !
 

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