Conventional dynamic comparator transistor sizing

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qwerty99

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Is there a design methodology one can follow to design a conventional dynamic comparator?
 

Well the design constraints are the noise, speed, offset and power dissipation. For high speed, you will need minimum length transistors. The noise is mostly dominated by the input differential pair. So you have to do a PNOISE sim and keep increasing the width of input diff pair till you achieve your target. Similar exercise needs to be carried out for offset.
 

First step is to design the cross coupled NMOS and PMOS pairs.

You have to design them based on their mobilities. For example Wp = 2.5 Wn

Simulate only upper PMOS and NMOS and find the point where they are in the middle (VDD/2) by playing with their ratios.

Dont put large transistors since it will increase your parasitic capacitance. (around W= 5-10um)

Then, input transistors should be large enough to have high gm in order to increase sensitivity.

Also current tail is important in order to reach better gm but you should be careful with your power budget.

Comparator is a nonlinear block and actually there is no obvious calculation for it. All you need to do is optimizing it.
 
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