Control of interleaved buck converters, voltage-mode and/or current-mode.

Hello.

I am designing a high-current buck-converter and if I could choose to use a interleaved design it would make a big difference, but I don't know anything about the feedback control och interleaved converters. Honestly I don't know much about ordinary feedback control, but I am going to develop an digital control loop and which ever sort of converter I choose learning is an integral part of the development procedure.

The availability of synchronous buck MOSFET gate drivers, especially with integrated MOSFETs makes interleaving very usefull. And given the effects on output ripple as well as heat management makes it almost an irresistible option, but I have tried to look for resources for learning about interleaved feedback control but I can't find anything.

I can't even find a clear description about how interleaved feedback control is structured or the basic idea of what is done.

On simplified schematics you can see that feedback looks the same as it does for single converters but that the feedback from the two converters in a 2-phase interleaved converter are routed together.
Which I don't understand, in my speculations I will assume that it relates to a 2-phase interleaved synchronous buck-converter.

The PWM signal is shifted by 180 degrees, and the feedback information is collected and used to regulate the output. But how is it used?
Is the let''s say current compared and the two converters are regulated by not allowing ether one to exceed I_OUT(max)/2?

I lost my train of thought so I'll continue later but any leads to any resources or any notes on this would be great appriciated.

Regards

Well this report does look into it....you will find good info within it if you look

- - - Updated - - -

Also, beware of the potential demon that is reversing current in the sync buck inductor...there have been other posts on it in this forum roundabout dec 2015, jan 2016, feb 2016...it can happen on light load, and can get out of hand of not dealt with...of course some reversal of current is very often ok.....but you must be wary of it running away

- - - Updated - - -

I also send here the situation whereby a single buck in a paralleled “bank” of them, may unfortunately start boosting back to the input…..and this can be mitigated by making a low impedance copper plane as shown……….pdf schem and ltspice sim attached

To generate staggered pulses to interleaved converters... You can arrange a D flip-flop and logic gates.



Notice the two output pulses are staggered 180 degrees. Also notice they overlap.

You get variable duty cycle by dialing a reference voltage at the potentiometer. The above schematic is adjustable from 51 to 99 percent duty cycle. Substitute 'NOR' gates if you want 1 to 49 percent duty cycle.

If you want to interleave more than two converters, create a shift register by adding more D flip-flops and logic gates.

- - - Updated - - -

The above simulation illustrates a concept for manually adjusting duty cycle. A given reference voltage does not necessarily produce a predictable output voltage. If you want to adjust duty cycle automatically via feedback control, you can configure an op amp to sense output voltage, and produce a proper reference voltage.

Also, i hereby give you a app note (do not tell anyone, no one is supposed to see it), about a way of dong parallel SMPS's by having one SMPS doing the voltage output regulation, and then all the others simply "copy" that masters output current...it ensures you get curent sharing.

- - - Updated - - -

and of course, they can be interleave switched etc

- - - Updated - - -

it also gaurantees that none of the paralleled SMPS's ever start boosting current back in the opposite direction. (or ditto with respect to bucks in parallel)